JP2005086664A - Oscillation circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent parasitic oscillation generated by parallel capacity components of an oscillation element in a voltage controlled oscillation circuit using the oscillation element such as an SAW vibrator. <P>SOLUTION: The oscillation circuit comprises a serial resonance circuit including an oscillation element 110, a coil 120 and a varicap 130 which are connected in series; an inverting amplifier circuits 11 to 13 which are connected between both ends of the serial resonance circuit and perform oscillating operations when first and second power source potentials are supplied; power supply control circuits 21 to 23 which control supply of the first or the second power source potential to the inverting amplifier circuits according to control signals; and a control signal generation circuit 30 which generates the control signals so that amplitude of output signals of the inverting amplifier circuits is controlled at the time of starting and the amplitude of the output signals of the inverting amplification circuits gradually increases in a prescribed period after the starting. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a voltage-controlled oscillation circuit using an oscillation element such as a SAW (Surface Acoustic Wave) vibrator, a crystal vibrator, or a ceramic vibrator. Furthermore, the present invention relates to a semiconductor integrated circuit for realizing such an oscillation circuit.

  Conventionally, a configuration shown in FIG. 21 is known as a voltage-controlled oscillation circuit using a SAW vibrator. As shown in FIG. 21, this oscillation circuit includes a series-connected inverters 11 to 13, resistors 14 to 16, and a semiconductor integrated circuit 10 incorporating capacitors 17 to 19, an external SAW vibrator 110, The extension coil 120 and the varicap 130 are configured.

  The output signal of the inverter 13 is given a predetermined phase rotation by a series resonance circuit constituted by the SAW vibrator 110, the extension coil 120, and the varicap 130, and is fed back to the input of the inverter 11, thereby oscillating. Is done.

FIG. 22 shows an equivalent circuit of the SAW vibrator. As shown in FIG. 22, the equivalent circuit of the SAW vibrator is expressed by an inductance component L ₁ , a resistance component R ₁ , a capacitance component C ₁ connected in series, and a parallel capacitance component C ₀ connected in parallel thereto. Can do. The resonance frequency f _R of this SAW vibrator is expressed by the following equation, assuming C ₀ << C ₁ .
f _R = 1 / 2π√L ₁ C ₁

In the oscillation circuit shown in FIG. 21, the basic oscillation frequency f ₀ is determined by adding the influence of the extension coil 120 and the varicap 130 to the equivalent circuit of the SAW vibrator. The varicap 130 is a variable capacitance diode utilizing the fact that the junction capacitance of the diode reversely biased to the PN junction changes according to the applied reverse bias voltage, and the property that the junction capacitance decreases as the reverse bias voltage increases. have.

Here, the fundamental oscillation frequency f ₀ can be adjusted by applying the control voltage V _CONT to one end of the resistor 16 to change the capacitance of the varicap 130. However, when the parallel capacitance component C ₀ of the SAW vibrator 110 resonates with the extension coil 120, parasitic oscillation may occur at a frequency higher than the fundamental oscillation frequency f ₀ .

Assuming that the inductance of the extension coil 120 is L and the series combined capacity of the parallel capacitance component C ₀ of the SAW vibrator 110, the capacity of the varicap 130 and the capacity of the capacitor 17 is C, the parasitic oscillation frequency f _P is given by expressed.
f _P = 1 / 2π√LC
When parasitic oscillation occurs at such a frequency, the original basic oscillation frequency f ₀ of the oscillation circuit cannot be obtained, and an external circuit that operates based on the output signal of the oscillation circuit malfunctions.

As a related technique, Patent Document 1 below describes an integrated circuit for a voltage controlled oscillator that improves the capacitance change efficiency of a varicap diode, has a large frequency adjustment width, and a small circuit scale. However, it does not describe prevention of parasitic oscillation caused by the parallel capacitance component of the oscillation element.
Japanese Patent Laid-Open No. 2002-246843 (first page, FIG. 1)

  Therefore, in view of the above points, an object of the present invention is to prevent parasitic oscillation generated by a parallel capacitance component of an oscillation element in a voltage-controlled oscillation circuit using an oscillation element such as a SAW vibrator. Furthermore, an object of the present invention is to provide a semiconductor integrated circuit for realizing such an oscillation circuit.

  In order to solve the above problems, an oscillation circuit according to a first aspect of the present invention includes a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and is connected between both ends of the series resonance circuit. An inverting amplifier circuit that oscillates when a power supply potential of 1 and a second power supply potential are supplied, and a power supply control circuit that controls the supply of the first or second power supply potential to the inverting amplifier circuit according to a control signal And a control signal generation circuit that generates a control signal so that the amplitude of the output signal of the inverting amplifier circuit is limited at the time of startup, and the amplitude of the output signal of the inverting amplifier circuit gradually increases in a predetermined period after startup. To do.

  Here, the inverting amplifier circuit may include a plurality of inverters connected in series. The power supply control circuit may include at least one transistor that controls supply of the first or second power supply potential to at least one of the plurality of inverters, or the first power supply to all of the plurality of inverters. Alternatively, a transistor for controlling the supply of the second power supply potential may be included. Alternatively, the power supply control circuit includes at least one first transistor for controlling supply of the first power supply potential to at least one of the plurality of inverters, and a second for at least one of the plurality of inverters. It may include at least one second transistor that controls supply of the power supply potential.

  An oscillation circuit according to a second aspect of the present invention includes a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and is connected between both ends of the series resonance circuit. The inverting amplifier circuit that oscillates when the power supply potential is supplied and the amplitude of the output signal of the inverting amplifier circuit are limited at startup, and the amplitude of the output signal of the inverting amplifier circuit gradually increases during a predetermined period after startup As described above, a power supply potential supply circuit that delays the first or second power supply potential and supplies it to the inverting amplifier circuit is provided.

  An oscillation circuit according to a third aspect of the present invention includes a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and is connected between both ends of the series resonance circuit. The AC amplitude of the oscillation signal is controlled at any point in the oscillation loop composed of the inverting amplifier circuit that oscillates when the power supply potential is supplied and the series resonance circuit and the inverting amplifier circuit according to the control signal And a control signal generation circuit that generates a control signal such that the AC amplitude of the oscillation signal is limited at the time of startup and the AC amplitude of the oscillation signal gradually increases during a predetermined period after startup.

  An oscillation circuit according to a fourth aspect of the present invention includes a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and is connected between both ends of the series resonance circuit. An inverting amplifier circuit that oscillates when a power supply potential of 1 is supplied, a pull-up / down circuit that pulls up or down one end of the varicap according to a control signal, and one end of the varicap that is pulled up or down at startup And a control signal generation circuit that generates a control signal so that the control voltage applied to the varicap gradually approaches a steady value in a predetermined period after activation.

  In the above, the oscillation circuit includes a first capacitor connected between the input terminal of the inverting amplifier circuit and the reference potential, and a second capacitor connected between the output terminal of the inverting amplifier circuit and the reference potential. May be further provided. The oscillation circuit may further include a feedback element that is connected between the input and output terminals of the inverting amplifier circuit and feeds back at least a DC signal. As the oscillation element, a surface acoustic wave vibrator, a crystal vibrator, or a ceramic vibrator can be used.

  Furthermore, the semiconductor integrated circuit according to the first aspect of the present invention is connected between both ends of a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and has a first power supply potential and a second power supply. An inverting amplifier circuit that oscillates when a potential is supplied, a power supply control circuit that controls the supply of the first or second power supply potential to the inverting amplifier circuit according to a control signal, and an output of the inverting amplifier circuit at startup And a control signal generation circuit that generates a control signal so that the amplitude of the signal is limited and the amplitude of the output signal of the inverting amplifier circuit gradually increases in a predetermined period after activation.

  A semiconductor integrated circuit according to a second aspect of the present invention is connected between both ends of a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and the first power supply potential and the second power supply potential are Inverting amplifier circuit that oscillates when supplied, and the amplitude of the output signal of the inverting amplifier circuit at startup is limited, and the amplitude of the output signal of the inverting amplifier circuit gradually increases in a predetermined period after startup, A power supply potential supply circuit that delays the first or second power supply potential and supplies the delayed power supply potential to the inverting amplifier circuit.

  A semiconductor integrated circuit according to a third aspect of the present invention is connected between both ends of a series resonant circuit including an oscillation element, a coil, and a varicap connected in series, and the first power supply potential and the second power supply potential are An inverting amplifier circuit that oscillates when supplied, and an amplitude control circuit that controls the AC amplitude of the oscillation signal at any point in the oscillation loop configured by the series resonance circuit and the inverting amplifier circuit according to the control signal And a control signal generation circuit that generates a control signal so that the AC amplitude of the oscillation signal is limited at the time of startup and the AC amplitude of the oscillation signal gradually increases in a predetermined period after startup.

  A semiconductor integrated circuit according to a fourth aspect of the present invention is connected between both ends of a series resonant circuit including an oscillation element, a coil, and a varicap connected in series, and the first power supply potential and the second power supply potential are Inverting amplifier circuit that oscillates when supplied, pull-up / down circuit that pulls up or down one end of the varicap according to the control signal, and one end of the varicap is pulled up or pulled down at startup And a control signal generation circuit for generating a control signal so that the control voltage applied to the varicap gradually approaches a steady value during the predetermined period.

  According to the first and second aspects of the present invention, by adjusting the supply of the power supply potential to the inverting amplifier circuit, the amplitude of the output signal of the inverting amplifier circuit is limited at the start-up, and is inverted during a predetermined period after the start-up. By making the amplitude of the output signal of the amplifier circuit gradually increase, it is possible to prevent parasitic oscillation caused by the parallel capacitance component of the oscillation element.

  Further, according to the third aspect of the present invention, by controlling the AC amplitude of the oscillation signal at any point in the oscillation loop, the AC amplitude of the oscillation signal is limited at startup, and a predetermined period after startup Thus, the parasitic amplitude generated by the parallel capacitance component of the oscillation element can be prevented by gradually increasing the AC amplitude of the oscillation signal.

  Further, according to the fourth aspect of the present invention, by pulling up or pulling down one end of the varicap, one end of the varicap is pulled up or pulled down at the start-up and applied to the varicap during a predetermined period after the start-up. As a result, the control voltage gradually approaches the steady state value, thereby preventing the parasitic oscillation caused by the parallel capacitance component of the oscillation element.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a diagram showing a configuration of an oscillation circuit according to the first embodiment of the present invention. As shown in FIG. 1, the oscillation circuit includes a semiconductor integrated circuit 100, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  Semiconductor integrated circuit 100 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, P-channel MOS transistors 21 to 23, and a control signal generation circuit 30. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistors 21 to 23 constitute a power supply control circuit that controls supply of power to the inverting amplifier circuit.

  Here, inverter 11 is formed of P channel MOS transistor 11a and N channel MOS transistor 11b, inverter 12 is formed of P channel MOS transistor 12a and N channel MOS transistor 12b, and inverter 13 is formed of P channel MOS transistor. A transistor 13a and an N-channel MOS transistor 13b are included.

The sources / drains of the transistors 21 to 23 constituting the power supply control circuit are respectively connected between the power supply potential V _DD and the sources of the P channel MOS transistors 11a to 13a included in the inverting amplifier circuit. The sources of the N-channel MOS transistors 11b to 13b included in the inverting amplifier circuit are connected to a power supply potential V _SS (which is a ground potential in this embodiment).

Note that the number of transistors connected between the power supply potential V _DD and the inverting amplifier circuit may be any one of the transistors 21 to 23 or two. In addition, the sources of the transistors 11a to 13a of the inverting amplifier circuit may be connected to each other so that one transistor is connected between the power supply potential V _DD and those sources.

The resistor 14 is connected between the input terminal of the inverter 11 and the output terminal of the inverter 13 and has a role as a feedback element that feeds back at least a DC signal. In addition, you may make it connect each feedback element (resistor etc.) between each input-output terminal of the inverters 11-13. One ends of resistors 15 and 16 are connected to both ends of the varicap 130, the other end of the resistor 15 is grounded, and a control voltage V _CONT is applied to the other end of the resistor 16.

  The capacitor 17 is a coupling capacitor for cutting a direct current component between the output terminal of the inverter 13 and the cathode terminal of the varicap 130. The capacitor 18 is connected between the input terminal of the inverter 11 and a reference potential (in this embodiment, the ground potential), and the capacitor 19 is connected between the output terminal of the inverter 13 and the reference potential. .

The output signal of the inverter 13 is given a predetermined phase rotation by a series resonance circuit constituted by the SAW vibrator 110, the extension coil 120, and the varicap 130, and is fed back to the input of the inverter 11, thereby oscillating. Is done. In this oscillation circuit, the basic oscillation frequency f ₀ is determined by adding the influence of the extension coil 120 and the varicap 130 to the equivalent circuit of the SAW vibrator shown in FIG.

The varicap 130 is a variable capacitance diode utilizing the fact that the junction capacitance of the diode reversely biased to the PN junction changes according to the applied reverse bias voltage, and the property that the junction capacitance decreases as the reverse bias voltage increases. have. Here, by adjusting the capacitance of the varicap 130 by applying a control voltage V _CONT, it is possible to control the fundamental oscillation frequency f _0.

However, when the parallel capacitance component C ₀ of the SAW vibrator 110 resonates with the extension coil 120, parasitic oscillation may occur at a frequency f _P higher than the fundamental oscillation frequency f ₀ . This parasitic oscillation is caused when the loop gain of the oscillation loop formed by the inverters 11 to 13 and the series resonance circuit is large at the time of starting the oscillation circuit. Also, once the oscillation is started using the original fundamental oscillation frequency f ₀ of the oscillator circuit, no parasitic oscillation is caused.

Therefore, in the present embodiment, the control signal generating circuit 30 generates a gate potential V _PG supplied to the transistors 21 to 23 constituting the power supply control circuit as a control signal, these transistors 21 to 23, The supply of the power supply potential V _{DD to} the inverters 11 to 13 is controlled.

FIG. 2 shows a change in the gate potential _VPG used as the control signal. When the semiconductor integrated circuit is activated by the rise of the power supply potential V _{DD at} time t ₀ , the gate potential V _PG once goes high, and the transistors 21 to 23 are turned off, so that the inverters 11 to 13 do not operate. Thereafter, the gate potential _VPG gradually decreases to a low level, and the transistors 21 to 23 are turned on, so that the inverters 11 to 13 start to operate, and the amplitude of the output signal of the inverter 13 gradually increases.

FIG. 3 shows the relationship between the oscillation loop gain G and the oscillation frequency f in the oscillation circuit according to this embodiment. When the oscillation loop gain G is small, the oscillation frequency f is also low, and when the oscillation loop gain G is large, the oscillation frequency f is also high. Here, parasitic oscillation frequency f _P is the frequency higher than the fundamental oscillation frequency f _0, if not oscillation loop gain G is increased, no parasitic oscillation is caused.

In the oscillation circuit according to the present embodiment, the gate potential V _{PG is set} to a high level at the time of start-up, and the oscillation loop gain G is controlled to decrease, and the gate potential V _PG is lowered for a predetermined period after the start-up to oscillate. is controlled so that the loop gain G gradually increases, enters the stable steady state by the oscillation frequency f reaches the fundamental oscillation frequency f ₀ becomes gradually higher. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a diagram showing a configuration of an oscillation circuit according to the second embodiment of the present invention. As shown in FIG. 4, the oscillation circuit includes a semiconductor integrated circuit 101, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 101 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, P channel MOS transistors 21 to 23, and a control signal generation circuit 30. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistors 21 to 23 constitute a power supply control circuit that controls supply of power to the inverting amplifier circuit.

The sources / drains of the transistors 21 to 23 constituting the power supply control circuit are connected to the sources of the N-channel MOS transistors 11b to 13b included in the inverting amplifier circuit and the power supply potential V _SS (in this embodiment, the ground potential) ) Are connected to each other. The sources of P-channel MOS transistors 11a to 13a included in the inverting amplifier circuit are connected to the power supply potential V _DD .

The transistor connected between the inverting amplifier circuit and the power supply potential V _SS is may be the one of the transistors 21 to 23, be two good. Also, by connecting the source of transistor 11b~13b of the inverting amplifier circuit to each other, between their source and the power source potential V _SS, it may be connected to one transistor.

In the present embodiment, the control signal generating circuit 30 generates a gate potential _{V PG} supplied to the transistors 21 to 23 constituting the power supply control circuit as a control signal, these transistors 21 to 23, the inverter 11 and controls the supply of the power supply potential _{V SS} against to 13.

That is, in the oscillation circuit according to the present embodiment, the gate potential V _PG is controlled to be high level at the time of startup so that the oscillation loop gain G is reduced, and the gate potential V _PG is lowered in a predetermined period after startup. Thus, the oscillation loop gain G is controlled to gradually increase, and when the oscillation frequency f gradually increases and reaches the fundamental oscillation frequency f ₀ , a stable steady state is entered. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a third embodiment of the present invention will be described.
FIG. 5 is a diagram showing a configuration of an oscillation circuit according to the third embodiment of the present invention. As shown in FIG. 5, the oscillation circuit includes a semiconductor integrated circuit 102, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 102 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, N-channel MOS transistors 41 to 43, and a control signal generation circuit 31. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistors 41 to 43 constitute a power supply control circuit that controls supply of power to the inverting amplifier circuit.

The drains / sources of the transistors 41 to 43 constituting the power supply control circuit are the same as the source of the N-channel MOS transistors 11b to 13b included in the inverting amplifier circuit and the power supply potential V _SS (in this embodiment, the ground potential) ) Are connected to each other. The sources of P-channel MOS transistors 11a to 13a included in the inverting amplifier circuit are connected to the power supply potential V _DD .

The transistor connected between the inverting amplifier circuit and the power supply potential V _SS is may be the one of the transistors 41 to 43, be two good. Also, by connecting the source of transistor 11b~13b of the inverting amplifier circuit to each other, between their source and the power source potential V _SS, it may be connected to one transistor.

In the present embodiment, the control signal generation circuit 31 generates the gate potential V _NG supplied to the transistors 41 to 43 constituting the power supply control circuit as a control signal. and controls the supply of the power supply potential _{V SS} against to 13.

FIG. 6 shows a change in the gate potential V _NG used as the control signal. When the semiconductor integrated circuit is activated by the rise of the power supply potential V _{DD at} time t ₀ , the gate potential V _NG is at a low level and the transistors 41 to 43 are turned off, so that the inverters 11 to 13 do not operate. . Thereafter, the gate potential V _NG gradually rises to a high level, and the transistors 41 to 43 are turned on, so that the inverters 11 to 13 start to operate, and the amplitude of the output signal of the inverter 13 gradually increases.

FIG. 7 shows the relationship between the oscillation loop gain G and the oscillation frequency f in the oscillation circuit according to this embodiment. When the oscillation loop gain G is small, the oscillation frequency f is also low, and when the oscillation loop gain G is large, the oscillation frequency f is also high. Here, parasitic oscillation frequency f _P is the frequency higher than the fundamental oscillation frequency f _0, if not oscillation loop gain G is increased, no parasitic oscillation is caused.

In the oscillation circuit according to the present embodiment, the gate potential V _{NG is set} to a low level at the time of startup to control the oscillation loop gain G to be small, and the gate potential V _NG is raised for a predetermined period after startup to oscillate. is controlled so that the loop gain G gradually increases, enters the stable steady state by the oscillation frequency f reaches the fundamental oscillation frequency f ₀ becomes gradually higher. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a fourth embodiment of the present invention will be described.
FIG. 8 is a diagram showing a configuration of an oscillation circuit according to the fourth embodiment of the present invention. As shown in FIG. 8, the oscillation circuit includes a semiconductor integrated circuit 103, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 103 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, N-channel MOS transistors 41 to 43, and a control signal generation circuit 31. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistors 41 to 43 constitute a power supply control circuit that controls supply of power to the inverting amplifier circuit.

The drains / sources of the transistors 41 to 43 constituting the power supply control circuit are respectively connected between the power supply potential V _DD and the sources of the P channel MOS transistors 11a to 13a included in the inverting amplifier circuit. The sources of the N-channel MOS transistors 11b to 13b included in the inverting amplifier circuit are connected to a power supply potential V _SS (which is a ground potential in this embodiment).

Note that the number of transistors connected between the power supply potential V _DD and the inverting amplifier circuit may be any one of the transistors 41 to 43, or two. In addition, the sources of the transistors 11a to 13a of the inverting amplifier circuit may be connected to each other so that one transistor is connected between the power supply potential V _DD and those sources.

In the present embodiment, the control signal generation circuit 31 generates the gate potential V _NG supplied to the transistors 41 to 43 constituting the power supply control circuit as a control signal. The supply of the power supply potential V _{DD to} ˜13 is controlled.

That is, in the oscillation circuit according to the present embodiment, the gate potential V _NG is controlled to be low level at the time of startup so that the oscillation loop gain G is decreased, and the gate potential V _NG is increased in a predetermined period after startup. Thus, the oscillation loop gain G is controlled to gradually increase, and when the oscillation frequency f gradually increases and reaches the fundamental oscillation frequency f ₀ , a stable steady state is entered. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a fifth embodiment of the present invention will be described.
FIG. 9 is a diagram showing a configuration of an oscillation circuit according to the fifth embodiment of the present invention. As shown in FIG. 9, the oscillation circuit includes a semiconductor integrated circuit 104, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  Semiconductor integrated circuit 104 includes inverters 11-13 connected in series, resistors 14-16, capacitors 17-19, P-channel MOS transistors 21-23, N-channel MOS transistors 41-43, and a control signal generation circuit. 32. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistors 21 to 23 and 41 to 43 constitute a power supply control circuit that controls supply of power to the inverting amplifier circuit.

The sources / drains of the transistors 21 to 23 constituting the power supply control circuit are respectively connected between the power supply potential V _DD and the sources of the P channel MOS transistors 11a to 13a included in the inverting amplifier circuit. The drains / sources of the transistors 41 to 43 constituting the power supply control circuit are the same as the source of the N-channel MOS transistors 11b to 13b included in the inverting amplifier circuit and the power supply potential V _SS (in this embodiment, the ground potential). Are connected to each other.

Note that the number of transistors connected between the power supply potential V _DD and the inverting amplifier circuit may be any one of the transistors 21 to 23 or two. In addition, the sources of the transistors 11a to 13a of the inverting amplifier circuit may be connected to each other so that one transistor is connected between the power supply potential V _DD and those sources.

Similarly, transistor connected between the inverting amplifier circuit and the power supply potential V _SS is may be the one of the transistors 41 to 43, be two good. Also, by connecting the source of transistor 11b~13b of the inverting amplifier circuit to each other, between their source and the power source potential V _SS, it may be connected to one transistor.

In the present embodiment, the control signal generating circuit 32 constitute the gate potential V _PG supplied to the transistors 21 to 23 constituting the power supply control circuit so as to generate a first control signal, the power supply control circuit transistor The transistors 21 to 23 and 41 to 43 control the supply of the power supply potentials V _DD and V _{SS to} the inverters 11 to 13 by generating the gate potential V _NG to be supplied to 41 to 43 as the second control signal. doing.

In other words, in the oscillation circuit according to the present embodiment, the gate potential V _{PG is set} to a high level at the time of startup and the gate potential V _{NG is set} to a low level to control the oscillation loop gain G to be small. The oscillation loop gain G is controlled to gradually increase by lowering the gate potential V _PG and increasing the gate potential V _NG during the period, and the oscillation frequency f gradually increases to reach the basic oscillation frequency f _0. To enter a stable steady state. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a sixth embodiment of the present invention will be described.
FIG. 10 is a diagram showing a configuration of an oscillation circuit according to the sixth embodiment of the present invention. As shown in FIG. 10, the oscillation circuit includes a semiconductor integrated circuit 105, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 105 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, an operational amplifier 50, a resistor 51, and a capacitor 52. The inverters 11 to 13 constitute an inverting amplifier circuit, and the operational amplifier 50, the resistor 51, and the capacitor 52 constitute a power supply control circuit that controls supply of power to the inverting amplifier circuit.

In the power supply control circuit, the resistor 51 is connected between the power supply potential V _DD and the non-inverting input terminal of the operational amplifier 50, and the capacitor 52 is connected to the non-inverting input terminal of the operational amplifier 50 and the power supply potential V _SS (in this embodiment). Is connected to the ground potential). The output potential V _O of the operational amplifier 50 is supplied to the sources of the P-channel MOS transistors 11a to 13a included in the inverting amplifier circuit and fed back to the inverting input terminal of the operational amplifier 50. As a result, the output potential V _O of the operational amplifier 50 becomes substantially equal to the potential at the non-inverting input terminal of the operational amplifier 50.

FIG. 11 shows changes in the output potential V _O of the operational amplifier. Even if the semiconductor integrated circuit is activated by the rise of the power supply potential V _{DD at} time t ₀ , the output potential V _O of the operational amplifier 50 is at a low level, and the inverters 11 to 13 do not operate. Thereafter, the non-inverting input terminal of the operational amplifier 50 is charged according to the time constant determined by the resistor 51 and the capacitor 52, and the potential rises, and the output potential V _O of the operational amplifier 50 gradually rises accordingly. As a result, the inverters 11 to 13 start to operate, and the amplitude of the output signal of the inverter 43 gradually increases.

FIG. 12 shows the relationship between the oscillation loop gain G and the oscillation frequency f in the oscillation circuit according to this embodiment. When the oscillation loop gain G is small, the oscillation frequency f is also low, and when the oscillation loop gain G is large, the oscillation frequency f is also high. Here, parasitic oscillation frequency f _P is the frequency higher than the fundamental oscillation frequency f _0, if not oscillation loop gain G is increased, no parasitic oscillation is caused.

In the oscillation circuit according to the present embodiment, the output potential V _{O of the} operational amplifier is set to a low level at the time of startup, and the oscillation loop gain G is controlled to be small, and the output potential V _O of the operational amplifier is increased during a predetermined period after startup. It is controlled so that the oscillation loop gain G by gradually increases, enters the stable steady state by the oscillation frequency f reaches the fundamental oscillation frequency f ₀ becomes gradually higher. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a seventh embodiment of the present invention will be described.
FIG. 13 is a diagram showing a configuration of an oscillation circuit according to the seventh embodiment of the present invention. As shown in FIG. 13, this oscillation circuit includes a semiconductor integrated circuit 106, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 106 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, an N channel MOS transistor 44, and a control signal generation circuit 33. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistor 44 constitutes a pull-down circuit that pulls down the input terminal of the inverter 11.

In the present embodiment, the drain / source of the transistor 44 of the pull-down circuit is connected between the input terminal of the inverter 11 and the power supply potential V _SS (in this embodiment, the ground potential). Control signal generating circuit 33, by generating the gate potential V _PD supplied to the transistor 44 of the pull-down circuit as a control signal, the transistor 44, the AC amplitude of the oscillation signal V ₁₁ at the input terminal of the inverter 11 is controlled.

FIG. 14 shows changes in the gate potential V _PD and the oscillation signal V ₁₁ used as control signals. When the semiconductor integrated circuit is activated by the rise of the power supply potential V _{DD at} time t ₀ , the gate potential V _PD once goes high, the transistor 44 is turned on, and the oscillation signal V _{11 at} the input terminal of the inverter 11 is turned on. AC amplitude is limited. Thereafter, the gate potential V _PD gradually decreases to a low level, and the transistor 44 shifts to an off state, so that the AC amplitude of the oscillation signal V ₁₁ gradually increases.

That is, in the oscillation circuit according to the present embodiment, the gate potential V _{PD is set} to a high level at the time of start-up, and the oscillation loop gain G is controlled to be small, and the gate potential V _PD is lowered in a predetermined period after the start-up. Thus, the oscillation loop gain G is controlled to gradually increase, and when the oscillation frequency f gradually increases and reaches the fundamental oscillation frequency f ₀ , a stable steady state is entered. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, an eighth embodiment of the present invention will be described.
FIG. 15 is a diagram showing a configuration of an oscillation circuit according to the eighth embodiment of the present invention. As shown in FIG. 15, the oscillation circuit includes a semiconductor integrated circuit 107, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 107 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, a P-channel MOS transistor 24, and a control signal generation circuit 34. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistor 24 constitutes a pull-up circuit that pulls up the input terminal of the inverter 11.

In the present embodiment, the source / drain of the transistor 24 of the pull-up circuit is connected between the power supply potential V _DD and the input terminal of the inverter 11. Control signal generating circuit 34, by generating the gate potential V _PU supplied to the transistor 24 of the pull-up circuit as a control signal, the transistor 24, the AC amplitude of the oscillation signal V ₁₁ at the input terminal of the inverter 11 is controlled .

FIG. 16 shows changes in the gate potential V _PU used as the control signal and the oscillation signal V ₁₁ . When the semiconductor integrated circuit is activated by the rise of the power supply potential V _{DD at} time t ₀ , the gate potential V _PU is at a low level, the transistor 24 is turned on, and the oscillation signal V at the input terminal of the inverter 11 is turned on. ₁₁ AC amplitude is limited. Thereafter, the gate potential V _PD gradually rises to a high level, and the transistor 24 shifts to an off state, so that the alternating current amplitude of the oscillation signal V ₁₁ gradually increases.

That is, in the oscillation circuit according to the present embodiment, the gate potential V _PU is controlled to be low level at the time of startup so that the oscillation loop gain G is decreased, and the gate potential V _PU is increased during a predetermined period after startup. It is controlled so that the oscillation loop gain G gradually increases, the entering stable steady state by the oscillation frequency f reaches the fundamental oscillation frequency f ₀ becomes gradually higher. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a ninth embodiment of the present invention will be described.
FIG. 17 is a diagram showing a configuration of an oscillation circuit according to the ninth embodiment of the present invention. As shown in FIG. 17, the oscillation circuit includes a semiconductor integrated circuit 109, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 109 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, an N channel MOS transistor 45, and a control signal generation circuit 36. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistor 45 constitutes a pull-down circuit that pulls down the anode terminal of the varicap 130.

In the present embodiment, the source / drain of the transistor 45 of the pull-down circuit is connected between the anode terminal of the varicap 130 and the power supply potential V _SS (in this embodiment, the ground potential). The control signal generation circuit 36 generates the gate potential _VPD supplied to the transistor 45 of the pull-down circuit as a control signal, whereby the anode potential V _A of the varicap 130 is controlled by the transistor 45.

FIG. 18 shows changes in the gate potential V _PD and the anode potential V _A used as control signals. When the semiconductor integrated circuit is activated by the rise of the power supply potential V _{DD at} time t ₀ , the gate potential V _PD is once set to the high level, the transistor 45 is turned on, and the anode potential V _A is pulled down to the low level. In addition, the AC amplitude of the oscillation signal is limited. Thereafter, the gate potential V _PD gradually decreases to a low level, and the transistor 45 shifts to an off state. Therefore, the anode potential V _A gradually approaches a steady value, and the AC amplitude of the oscillation signal gradually increases.

That is, in the oscillation circuit according to the present embodiment, the anode potential V _A is controlled to be pulled down at startup and controlled so as to approach a steady-state value of the anode potential V _A in a predetermined period after startup, the oscillation enter the stable steady state by the frequency f reaches the fundamental oscillation frequency f ₀ becomes gradually higher. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

Next, a tenth embodiment of the present invention will be described.
FIG. 19 is a diagram showing a configuration of an oscillation circuit according to the tenth embodiment of the present invention. As shown in FIG. 19, the oscillation circuit includes a semiconductor integrated circuit 108, an external SAW vibrator 110, an extension coil 120, and a varicap 130.

  The semiconductor integrated circuit 108 includes inverters 11 to 13 connected in series, resistors 14 to 16, capacitors 17 to 19, a P-channel MOS transistor 25, and a control signal generation circuit 35. The inverters 11 to 13 constitute an inverting amplifier circuit, and the transistor 25 constitutes a pull-up circuit that pulls up the cathode terminal of the varicap 130.

In the present embodiment, the source / drain of the transistor 25 of the pull-up circuit is connected between the power supply potential V _DD and the cathode terminal of the varicap 130. Control signal generating circuit 35, by generating the gate potential V _PU supplied to the transistor 25 of the pull-up circuit as a control signal, the transistor 25, the cathode potential V _C of the varicap 130 is controlled.

Figure 20 shows the gate potential _{V PU} used as a control signal, and the change in the cathode potential _{V C.} When the semiconductor integrated circuit by the power supply potential V _DD rises is started at time t _0, the gate potential V _PU is at a low level, the transistor 25 is turned on, pull-cathode potential V _C is at the high level And the AC amplitude of the oscillation signal is limited. Thereafter, the gate potential V _PU gradually rises to a high level, and the high level transistor 25 shifts to an off state. Therefore, the cathode potential V _C gradually approaches a steady value and the AC amplitude of the oscillation signal gradually increases.

That is, in the oscillation circuit according to the present embodiment, the cathode potential V _C is controlled to be pulled up, and controlled so as to approach a steady-state value of the cathode potential V _C at a predetermined period after start at startup, enter the stable steady state by the oscillation frequency f reaches the fundamental oscillation frequency f ₀ becomes gradually higher. Therefore, a situation in which the oscillation loop gain G becomes larger than necessary and parasitic oscillation is caused does not occur.

  INDUSTRIAL APPLICABILITY The present invention can be used in a voltage control type oscillation circuit using an oscillation element such as a SAW resonator, a crystal resonator, or a ceramic resonator, and a semiconductor integrated circuit for realizing such an oscillation circuit. Is possible.

The figure which shows the structure of the oscillation circuit which concerns on the 1st Embodiment of this invention. The figure which shows the change of the gate potential _VPG in the 1st Embodiment of this invention. The figure which shows the relationship between the oscillation loop gain G and the oscillation frequency f in the 1st Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 2nd Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 3rd Embodiment of this invention. The figure which shows the change of the gate potential _VNG in the 3rd Embodiment of this invention. The figure which shows the relationship between the oscillation loop gain G and the oscillation frequency f of an oscillation circuit in the 3rd Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 4th Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 5th Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 6th Embodiment of this invention. 6 shows the change of the operational amplifier output voltage V _O in the embodiment of the present invention. The figure which shows the relationship between the oscillation loop gain G and the oscillation frequency f of an oscillation circuit in the 6th Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 7th Embodiment of this invention. 7 shows a change in gate potential V _PD and the oscillation signal V ₁₁ in the embodiment of the present invention. The figure which shows the structure of the oscillation circuit which concerns on the 8th Embodiment of this invention. Shows a variation of the eighth gate potential V _PU and the oscillation signal V ₁₁ in the embodiment of the present invention. The figure which shows the structure of the oscillation circuit which concerns on the 9th Embodiment of this invention. The figure which shows the change of the gate potential _VPD and anode potential _VA in the 9th Embodiment of this invention. The figure which shows the structure of the oscillation circuit which concerns on the 10th Embodiment of this invention. Shows the change in the gate potential V _PU and the cathode potential V _C in the tenth embodiment of the present invention. The figure which shows the structure of the conventional voltage control type | mold oscillation circuit using a SAW vibrator. The figure which shows the equivalent circuit of a SAW vibrator.

Explanation of symbols

11 to 13 inverter, 11a to 13a P channel MOS transistor, 11b to 13b N channel MOS transistor, 14 to 16 resistor, 17 to 19 capacitor, 21 to 25 P channel MOS transistor, 30 to 36 control signal generation circuit, 41 to 45 N channel MOS transistor, 100 semiconductor integrated circuit, 110 SAW vibrator, 120 extension coil, 130 varicap

Claims (15)

A series resonant circuit including an oscillation element, a coil, and a varicap connected in series;
An inverting amplifier circuit connected between both ends of the series resonance circuit and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
A power supply control circuit for controlling supply of the first or second power supply potential to the inverting amplifier circuit according to a control signal;
A control signal generating circuit that generates the control signal so that the amplitude of the output signal of the inverting amplifier circuit is limited at the time of startup, and the amplitude of the output signal of the inverting amplifier circuit gradually increases during a predetermined period after startup;
An oscillation circuit comprising:   The oscillation circuit according to claim 1, wherein the inverting amplifier circuit includes a plurality of inverters connected in series.   The oscillation circuit according to claim 2, wherein the power supply control circuit includes at least one transistor that controls supply of a first or second power supply potential to at least one of the plurality of inverters.   The oscillation circuit according to claim 2, wherein the power supply control circuit includes a transistor that controls supply of the first or second power supply potential to all of the plurality of inverters. The power supply control circuit is
At least one first transistor for controlling supply of a first power supply potential to at least one of the plurality of inverters;
At least one second transistor for controlling supply of a second power supply potential to at least one of the plurality of inverters;
The oscillation circuit according to claim 2, comprising: A series resonant circuit including an oscillation element, a coil, and a varicap connected in series;
An inverting amplifier circuit connected between both ends of the series resonance circuit and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
The first or second power supply potential is delayed so that the amplitude of the output signal of the inverting amplifier circuit is limited at startup and the amplitude of the output signal of the inverting amplifier circuit gradually increases during a predetermined period after startup. A power supply potential supply circuit for supplying to the inverting amplifier circuit;
An oscillation circuit comprising: A series resonant circuit including an oscillation element, a coil, and a varicap connected in series;
An inverting amplifier circuit connected between both ends of the series resonance circuit and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
An amplitude control circuit for controlling the alternating current amplitude of the oscillation signal at any point in the oscillation loop constituted by the series resonance circuit and the inverting amplification circuit according to a control signal;
A control signal generating circuit that generates the control signal such that the AC amplitude of the oscillation signal is limited at the time of startup, and the AC amplitude of the oscillation signal gradually increases in a predetermined period after startup;
An oscillation circuit comprising: A series resonant circuit including an oscillation element, a coil, and a varicap connected in series;
An inverting amplifier circuit connected between both ends of the series resonance circuit and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
A pull-up / down circuit for pulling up or pulling down one end of the varicap according to a control signal;
A control signal generation circuit for generating the control signal so that one end of the varicap is pulled up or pulled down at the time of startup, and a control voltage applied to the varicap gradually approaches a steady value in a predetermined period after startup; ,
An oscillation circuit comprising: A first capacitor connected between an input terminal of the inverting amplifier circuit and a reference potential;
A second capacitor connected between the output terminal of the inverting amplifier circuit and a reference potential;
The oscillation circuit according to claim 1, further comprising:   The oscillation circuit according to claim 1, further comprising a feedback element connected between input / output terminals of the inverting amplifier circuit and feeding back at least a DC signal.   The oscillation circuit according to claim 1, wherein the oscillation element is a surface acoustic wave resonator, a crystal resonator, or a ceramic resonator. An inverting amplifier circuit connected between both ends of a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
A power supply control circuit for controlling supply of the first or second power supply potential to the inverting amplifier circuit according to a control signal;
A control signal generating circuit that generates the control signal so that the amplitude of the output signal of the inverting amplifier circuit is limited at the time of startup, and the amplitude of the output signal of the inverting amplifier circuit gradually increases during a predetermined period after startup;
A semiconductor integrated circuit comprising: An inverting amplifier circuit connected between both ends of a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
The first or second power supply potential is delayed so that the amplitude of the output signal of the inverting amplifier circuit is limited at startup and the amplitude of the output signal of the inverting amplifier circuit gradually increases during a predetermined period after startup. A power supply potential supply circuit for supplying to the inverting amplifier circuit;
A semiconductor integrated circuit comprising: An inverting amplifier circuit connected between both ends of a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
An amplitude control circuit for controlling the alternating current amplitude of the oscillation signal at any point in the oscillation loop constituted by the series resonance circuit and the inverting amplification circuit according to a control signal;
A control signal generating circuit that generates the control signal such that the AC amplitude of the oscillation signal is limited at the time of startup, and the AC amplitude of the oscillation signal gradually increases in a predetermined period after startup;
A semiconductor integrated circuit comprising: An inverting amplifier circuit connected between both ends of a series resonance circuit including an oscillation element, a coil, and a varicap connected in series, and performing an oscillation operation when a first power supply potential and a second power supply potential are supplied;
A pull-up / down circuit for pulling up or pulling down one end of the varicap according to a control signal;
A control signal generation circuit for generating the control signal so that one end of the varicap is pulled up or pulled down at the time of startup, and a control voltage applied to the varicap gradually approaches a steady value in a predetermined period after startup; ,
A semiconductor integrated circuit comprising:

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