JPH0548968B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation control circuit, and particularly to an oscillation control circuit that controls an internal oscillation circuit of a CMOS type semiconductor integrated circuit.

[Conventional technology]

In recent years, power consumption has been reduced in semiconductor integrated circuits, including CMOS type, and one way to do this is to temporarily stop oscillation when the oscillation output of the internal oscillation circuit is not needed, thereby reducing the power consumption of semiconductor integrated circuits as much as possible. is being carried out.

FIG. 2 is a circuit diagram showing an example of a conventional oscillation control circuit.

In this circuit, when a clock signal is supplied to the internal circuit 6 of the semiconductor integrated circuit by internal oscillation, a crystal oscillator 51 is connected between an external clock input terminal 52 and an output terminal 53. in this case,
Inverter 4, bias circuit 54, and crystal oscillator 5
1 constitutes an oscillation circuit 5, and a bias circuit 5
4, when the oscillation stop signal STOP is not present, the N-type and P-type transistors Q ₂ and Q ₃ of the switch circuit 2 become conductive, and the N of the inverter 4 is turned on through the resistance of the transistors Q ₂ and Q ₃ . A bias is applied to the type and P type transistors Q ₆ and Q ₇ to oscillate.

On the other hand, when the internal circuit 6 is driven by an external clock, the external clock signal CK is input from the external clock input terminal.

Furthermore, in this circuit, when a high-level oscillation stop signal STOP is received from the internal circuit 6, the N-type transistor _Q1 of the first switch circuit 1 becomes conductive, and the input terminal of the inverter 4 is fixed at a low level. , at the same time transistors Q ₂ and Q ₃ of the second switch circuit 2
is in a non-conductive state, the bias circuit 54 is opened, and the oscillation of the oscillation circuit 5 is stopped.

[Problem that the invention seeks to solve]

However, in the conventional oscillation control circuit described above, no particular problem occurs when operating using internal oscillation, but when operating using an external clock, the N-type transistor is turned off by the oscillation stop signal STOP from the internal circuit 6.
_Q1 becomes conductive and the input terminal of inverter 4 becomes low level, but even in this case, the external clock signal
Since CK continues to be supplied, the external clock signal
When CK is high level, external clock input terminal 5
The drawback is that a through current flows through the N-type transistor _Q1 , consuming power.

Furthermore, at this time, since the input terminal of the inverter 4 is at an intermediate level, neither low level nor high level, a through current also flows through the P-type and N-type transistors Q ₆ and Q ₇ that constitute the inverter 4, resulting in power consumption. It had the disadvantage of being rejected.

An object of the present invention is to reduce power consumption by cutting off the through current flowing from the external clock input terminal to the transistor of the first switch circuit and the through current flowing through the transistor of the inverter forming the oscillation circuit when the external clock is operated. An object of the present invention is to provide an oscillation control circuit that can reduce the oscillation.

[Means for solving problems]

The oscillation control circuit of the present invention includes an inverter that outputs a clock signal to be supplied to the internal circuit of a CMOS type semiconductor integrated circuit and serves as a component of the oscillation circuit, and an input terminal of the inverter that outputs a clock signal to be supplied to the internal circuit of a CMOS type semiconductor integrated circuit. a first switch circuit that fixes the oscillation circuit to one level and stops the oscillation circuit;
A second switch circuit is connected between the input end and the output end of the inverter and opens the bias circuit of the inverter in response to the oscillation stop signal, and an external clock signal that drives the internal circuit is connected to the input of the inverter. an oscillation control circuit having an external clock input terminal supplied to the first terminal;
A third switch circuit which is opened by the oscillation stop signal is provided between the connection point of the switch circuit and the input end of the inverter and the external clock input terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This embodiment differs from the conventional oscillation control circuit shown in FIG. The point is that a third switch circuit 3 is provided which is opened by the switch.

High level oscillation stop signal from internal circuit 6
Due to STOP, the N-type transistor _Q1 of the first switch circuit 1 becomes conductive, and the inverter 4
Fix the input terminal to low level. At the same time, the N-type and P-type transistors of the third switch circuit are
Since Q ₄ and Q ₅ become non-conductive, the external clock signal CK is cut off and does not reach the connection point between the input terminal of the inverter 4 and the transistor Q ₁ .

Therefore, even if the external clock signal CK becomes high level during operation using an external clock, the connection point between the input terminal of inverter 4 and transistor _Q1 remains low level, so that transistor _Q1 and inverter 4 are connected to each other. No through current flows through the constituent N-type and P-type transistors Q ₆ and Q ₇ .

〔Effect of the invention〕

As explained above, in the present invention, there is a
By providing a third switch circuit that is opened by the oscillation stop signal, when the external clock is operating,
It is possible to cut off the through current flowing from the external clock input terminal into the transistor of the first switch circuit and the through current flowing through the transistor of the inverter forming the oscillation circuit, thereby reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional oscillation control circuit. 1, 2, 3...Switch circuit, 4...Inverter, 5...Oscillation circuit, 6...Internal circuit, 21...
Inverter, 51...Crystal resonator, 52...External clock input terminal, 53...Output terminal, 54...
Bias circuit, _Q1 to _Q7 ...transistors.

Claims (1)

[Claims] 1 An inverter that outputs a clock signal to be supplied to the internal circuit of a CMOS type semiconductor integrated circuit and serves as a component of an oscillation circuit, and an input terminal of this inverter is fixed at one level by an oscillation stop signal from the internal circuit. a first switch circuit that stops the oscillation of the oscillation circuit; a second switch circuit that is connected between the input end and the output end of the inverter and opens the bias circuit of the inverter in response to the oscillation stop signal; In the oscillation control circuit, the oscillation control circuit has an external clock input terminal that supplies an external clock signal for driving the internal circuit to the input terminal of the inverter, and a connection point between the first switch circuit and the input terminal of the inverter and the external clock signal. An oscillation control circuit characterized in that a third switch circuit is provided between the input terminal and the third switch circuit to be opened by the oscillation stop signal.