JPH0553402B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation circuit mounted in an integrated circuit, and particularly to an oscillation circuit in which a mechanical resonator is connected to an external terminal.

[Conventional technology]

FIG. 4 is a diagram showing an example of an oscillation circuit in an integrated circuit according to the prior art. When an external mechanical resonator (for example, a crystal resonator) is connected between terminals A and B, an oscillation circuit is formed by this crystal resonator, the inverter gate 20, and the feedback resistor 1. The output of this oscillation circuit is the inverter gate 1
5 to terminal E. When terminal C is fixed at "low level", the output of inverter gate 20 forming the oscillation circuit is outputted to terminal F via NAND gates 17 and 19, and can be used as a clock source within the integrated circuit.

[Problems to be solved by the invention] In the oscillation circuit configured as shown in FIG. When input, the same output as that from this external oscillation circuit is obtained at terminal F. At this time, the output of the internal oscillation circuit composed of the mechanical resonator, the inverter gate 20, and the feedback resistor 1 is not output to the terminal F because it is blocked by the NAND gate 17, but is output through the inverter gate 15. It will be output to terminal E.

In this way, even when using the output from another oscillation circuit provided outside the integrated circuit, the internal oscillation circuit is always operating, so the current supplied to the load connected to terminal E and the internal The oscillation circuit has the disadvantage that current flows constantly and consumes a large amount of power.

Therefore, an object of the present invention is to eliminate the drawbacks of the above-mentioned conventional techniques and to provide a novel oscillation circuit with low power consumption.

In contrast to the conventional oscillator circuit described above, the present invention replaces the inverter gate used as an amplifier with a clocked inverter gate having an input gate that controls conduction and non-conduction states, and outputs an output from another external oscillation circuit. When using the integrated circuit, by stopping the operation of the internal oscillation circuit, the current consumed by the oscillation circuit itself, the inverter gate connected to the next stage of the oscillation circuit, and its load is reduced, and the current consumption within the integrated circuit is reduced. It has an original content that can significantly reduce power consumption.

[Means for solving problems]

The oscillation circuit of the present invention includes an oscillation section in which the input and output terminals of a clocked inverter are respectively connected to an external mechanical resonator, and an oscillation signal of the oscillation section and an external oscillation signal input from the outside. The clock generation circuit selects one of the clocks using a control signal from the outside and outputs the clock signal as a clock signal, and is configured to control conduction/non-conduction of the gate of the clocked inverter in accordance with the control signal.

〔Example〕

Next, embodiments of the oscillation circuit according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention. The first embodiment has a feedback resistor 1 and P
It is composed of channel transistors 2, 3, N-channel transistors 4, 5, 14, inverter gates 15, 16, and NAND gates 17-19. When terminal C is fixed at "low level", the clocked inverter gate composed of transistors 2 to 5 operates as an inverter,
This clocked inverter gate, external resonator, and feedback resistor 1 constitute an oscillation circuit, and the oscillation output is sent to terminal E via the inverter gate and 15, and to terminal F via NAND gates 17 and 19.
are output respectively.

Further, when the terminal C is fixed at a "high level", the clocked inverter gate constituted by transistors 2 to 5 is in a non-conductive state, that is, the output is in a high impedance state, and oscillation is stopped.
At the same time, the N-channel transistor 14 becomes conductive.
The gate of inverter 15 is fixed at "low level". On the other hand, at this time, the output of the NAND gate 17 is at "high level", and the output of the NAND gate 19 becomes the same as the input state of the terminal D, so
The input terminal of terminal D will be output.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention. Components with reference numerals 1 to 5 and 14 to 19 are all the same as in FIG.
It consists of 3. The above transistors 2 to 5, 6
-9 and 10-13 constitute first, second and third clocked inverter gates, respectively. An oscillation circuit is constituted by a circuit in which these three clocked inverter gates are connected in series, an external resonator, and a feedback resistor 1, and as in FIG.
The signals are then output to terminal F via NADA gates 17 and 19, respectively.

In this embodiment, there are three clocked inverter gates.
Since the stages are simply connected in series, the basic operation is exactly the same as in FIG. In this way, by connecting three stages of clocked inverter gates in series, the gain of the amplifier is much higher than that of a single stage configuration, so it is easy to use a mechanical resonator with high loss resistance. It will oscillate. Another advantage is that an oscillation output waveform close to a square wave can be obtained. Furthermore, by appropriately setting the size of the transistors in each stage of the three clocked inverter gates, it is possible to achieve even lower power consumption.

FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the present invention. 1-5, 7, 8, 11, 12, 14
All the components of ~19 are the same as in Figure 2, transistors 3 and 4, transistors 7 and 8,
Transistors 11 and 12 each constitute an inverter gate, and transistors 2 and 5 are used to control the conduction and non-conduction states of all three inverter gates. An oscillation circuit is constituted by a circuit in which these three inverter gates are connected in series, an external vibrator, and a feedback resistor 1, and its operation is exactly the same as that in FIG. 2, so a description thereof will be omitted.

However, compared to the circuit of Figure 2 which has three stages of clocked inverter gates connected in series, the oscillation circuit of Figure 3 requires only one set of transistors 2 and 5 to conduct the circuit which has three stages of inverter gates connected in series. And since the non-conducting state can be controlled, the number of transistors can be reduced by four. Therefore, there is an advantage that the area of the oscillation circuit portion on the integrated circuit chip can be reduced.

〔Effect of the invention〕

In the oscillation circuit configured as above,
If the control terminal C is fixed at a "low level", the circuit operates in the same way as a conventional oscillation circuit. When using an external signal, if you input the external signal to terminal D and fix control terminal C to "high level", the operation of the internal oscillation circuit will stop, so you can use the internal oscillation circuit itself and terminal E as output. The power consumption is reduced by the amount of current flowing through the load connected to the inverter gate 15 and the terminal E, which has the effect of significantly reducing power consumption within the integrated circuit.

In addition, by appropriately increasing the on-resistance of the P-channel transistor 2 and the N-channel transistor 5 of the clocked inverter gate composed of the transistors 2 to 5, it is possible to connect the transistors 2 to 5 from the power supply terminal V _DD when the internal oscillation circuit oscillates. It also has the effect of suppressing the current flowing into GND through 5 and contributing to a reduction in power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the oscillation circuit according to the present invention, FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the oscillation circuit according to the present invention, and FIG. 3 is a circuit diagram showing the configuration of the second embodiment of the oscillation circuit according to the present invention. FIG. 4 is a circuit diagram showing an example of an oscillation circuit according to the prior art. 1...Feedback resistance, 2, 3, 6, 7, 10, 11
...P channel transistor, 4, 5, 8,
9, 12, 13, 14... N channel transistor, 15, 16, 20... Inverter gate,
17, 18, 19...NAND gate, A~F...
...Terminal.

Claims (1)

[Claims] 1. An oscillating unit in which the input and output terminals of the clocked inverter are respectively connected to an external mechanical resonator, and either the oscillating signal of the oscillating unit or the external oscillating signal input from the outside is connected to an external mechanical oscillator. An oscillation device comprising: a clock generation circuit that selects a clock signal based on an input control signal and outputs the clock signal as a clock signal; and controls conduction/non-conduction of the gate of the clocked inverter according to the control signal. circuit.