JPS61214016A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a malfunction due to the collision of signals and to simplify the constitution of a processor by using a power supply terminal or an earth terminal as a stop request signal to a semiconductor integrated circuit IC device, and controlling directly a clock generating circuit. CONSTITUTION:A microprocessor stop request signal is supplied to a microprocessor 15 of an IC device consisting of an MMOS, and the clock issued from a clock generating circuit 16 is supplied to a clock input terminal CLK. While the processor 15 supplies a control signal to a control input terminal 16a of the circuit 16 from a power supply terminal 15a with inputting of the stop request signal and stops the clock supply to the processor 15 itself. The clock stop request signal CKSTP issued from an instruction executing part 17 of the processor 15 is supplied to an OR gate 18 and an NOR gate 19 with the reset signal RESET applied to the other side of the gate 18. Then the signal obtained by processing the output of the gate 18 through the NOR gates 20 and 22 is supplied to the other side of the gate 19, then supplied to the terminal 15a for prevention of collision of signals.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a 0MO8 type semiconductor integrated circuit device that is compatible with a semiconductor integrated circuit device configured with an N-channel type MO8FET and has low power consumption. This is particularly related to the terminal function.

[Technical background of the invention]

In recent years, in order to reduce the power consumption of semiconductor integrated circuit devices, such as microprocessors, NMO8 circuits have been replaced with CMO8 circuits.

Furthermore, in microprocessors, in order to further reduce power consumption, the clock is stopped in a low power consumption mode.

By the way, in order to convert a microprocessor made up of N-channel MOS FETs into a CMO8 circuit and provide a clock stop function while maintaining compatibility, the following steps are taken. That is, as shown in FIG. 5, an output port 13 is provided on the bus 12 connected to the microprocessor 1, and by executing the I10 instruction in the microprocessor 1, the clock is stopped at the output port 13. give information on. Then, in accordance with this information, the clock supply from the clock generation circuit 14 to the clock input terminal CLK of the microprocessor 11 is stopped.

[Problems with background technology]

However, the above method requires additional circuitry and additional terminals, such as providing the output port 13 to stop the clock. Furthermore, since the detailed timing for stopping the clock cannot be specified, it is necessary to configure the microprocessor 11 so that the clock can be stopped at any timing. As a result, the configuration of the microprocessor becomes complicated, and the chip area increases, making it expensive.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a semiconductor integrated circuit device that can simplify the additional circuit for stopping the clock, and can also simplify its own structure by transmitting the timing to stop the clock to the clock generation circuit. .

[Summary of the invention]

That is, in this invention, in order to achieve the above object, the power supply terminal or the ground terminal is used as a signal terminal indicating the stop state of the semiconductor integrated circuit device or a stop request signal terminal for the semiconductor integrated circuit device, and the clock generation circuit is designed to be directly controlled. At this time, in order to prevent malfunction due to signal collision, the output signal is fed back to make the output level the same as the external signal level, thereby preventing abnormal current from flowing.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. This invention has been made by focusing on the following points. LSIs with an NMO8 circuit configuration consume large amounts of power and often have multiple power supply terminals and multiple ground terminals, whereas LSIs with a CMO8 circuit configuration consume only one power supply terminal and one ground terminal each. You only need one bottle at a time.

The semiconductor integrated circuit device with the CMO8 circuit configuration is still compatible with the semiconductor integrated circuit device with the NMO8 configuration.
The terminals that were power supply terminals in the MO8 circuit must be formed so that they may be connected to the power supply, and the terminals that were ground terminals may be connected to the ground. However, when stopping the clock in low power consumption mode, there is no need to maintain compatibility.

This is because in an LSI having an NMO8 circuit configuration, the clock cannot be stopped due to the nature of the circuit. Therefore,
When configuring a circuit that stops the clock, the power supply terminal or the ground terminal remaining in the CMO8 circuit can be used as a signal output terminal indicating the stopped state of the semiconductor integrated circuit device. When using the power supply terminal or ground terminal as a signal output terminal in this way, in order to prevent malfunction due to signal collision, the output signal is fed back and the output level is made to be the same as the external signal level. To prevent abnormal current from flowing.

Figures 1 and 2 show the structure of the device that realizes the above functions.
As shown in the figure. Here, an explanation will be given using a microprocessor as an example of a semiconductor integrated circuit device. A clock is supplied from a clock generation circuit 16 to the clock input terminal CLK of the microprocessor 15 in FIG. and,
When the microprocessor stop request signal is supplied to the microprocessor 15, a control signal is supplied from the power supply terminal 15a of the microprocessor 15 to the control input terminal 16a of the clock generation circuit 160, and the clock supply to the microprocessor 15 is stopped. be done.

FIG. 2 shows an example of a partial circuit configuration within the microprocessor 15 for realizing the configuration shown in FIG. 1 above. The clock stop request signal CKSTP output from the instruction execution unit 17 is transmitted to the ORDART 18 and the NORDART 19.
are respectively supplied to one input terminal of the . The other input terminal of the OR gate 18 is supplied with a reset signal RESET. The output of the above ordart 18 is the output of nordart 2
0, and the inverter circuits 211 to 2 are supplied directly to the other input terminal of this NOR gate 20.
15. The output of the Nordart 20 is supplied to one input terminal of the Nordart 22, and the output of the Nordart 22 is supplied to the other input terminal of the Nordart 19. The output of the NOR gate 19 is supplied to the terminal 151L via the resistor 23, and is also supplied to the other input terminal of the NOR gate 22. The signal RESET is transmitted to the microprocessor 15.
This signal is at the "H" level during initialization, and is at the II L" level during normal operation. Further, the terminal 15a is connected to ground when maintaining compatibility with the NMO8 circuit, but is also used as a clock stop request signal output terminal. Clock stop request signal CKSTP output from the instruction execution unit 17
Normally, when the "L" level clock is stopped, it becomes a high level.

Next, the operation of the above configuration will be explained with reference to the timing charts of FIGS. 3 and 4. Terminal 15h is used as a clock stop request signal output terminal,
When in the output state (see Figure 3), time t1
When the reset signal RESET becomes °'L# level,
The output of the gate 2θ is maintained for a predetermined time (between times t2 and t3)
II H# level. With this, Noah Dart 2
The output of 2 is “L” level, and the output of Nordart 19 is ’H.
” level. At time t4, the clock stop request signal CK
When STP reaches °°H" level, Noah'r"-119
The output becomes '°L# level (time t5), and a clock stop request is issued. Next, the clock stop request signal CKST
When P goes to the "L" level (time t6), the NOADART 20 goes to the "H" level for a predetermined period of time (between times t7 and t9) and generates a pulse, and at time t8, the terminal 15a goes to the LH" level.
level.

On the other hand, when the terminal 15a is fixed at the ground level (see FIG. 4), the reset signal RESET is output at time t1.
falls, time t2. t3 current is prevented. Thereafter, the output of the NOR gate 22 becomes H'' level, and the output of the NOR gate 19 becomes LT L'' level, so that no signal collision occurs in the normal state. Next, when the instruction execution unit 17 is in a stopped state, the clock stop request signal CKSTP is set to "H".
After reaching level, it changes to °°L" level, the output of Nordart 20 becomes "H# level between times t4 and t6, p1 the output of Nordart 22 becomes 6L" level, and the output of Nordart 19 changes to °I HAl level. However, since these periods t5 and t7 are short, the reset signal RES
The fall of ET is not a problem, just like when it is shi.

This configuration has a wide range of applications because it maintains compatibility with the NMO8 circuit, and because the clock stop request signal can be directly given to the clock generation circuit, there is no need to provide an output port, etc. The circuit can be simplified. In addition, as mentioned above, since the clock stop/start signal is directly supplied to the clock generation circuit, the precise timing for stopping the clock can be set, and the clock can be stopped at a timing that is convenient for the microprocessor. can also be simplified.

In the above embodiments, a microprocessor is used as an example of the semiconductor integrated circuit device, but it goes without saying that other devices may be used. Further, although the case where the Norus generation circuit is controlled has been described, other circuits or devices may be used.

〔Effect of the invention〕

As explained above, according to the present invention, a semiconductor integrated circuit device is provided which can simplify the additional circuit for stopping the clock, and can also simplify its own structure by transmitting the timing to stop the clock to the clock generation circuit. It will be done.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram for explaining a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a circuit configuration for realizing the configuration of FIG. 1, and FIG.
4 and 4 are timing charts for explaining the operation of the circuit shown in FIG. 2, respectively, and FIG. 5 is a diagram for explaining the conventional semiconductor integrated circuit device. =10- 15...Microprocessor, 15a...Terminal, 16
. . . Clock generation circuit, 17 . . . Instruction execution unit, 23
...Resistance (loading means).

Claims (1)

[Claims] In a semiconductor integrated circuit device that has an output terminal that informs the internal state to the outside, the signal level of the output terminal is maintained when there is no change in the internal signal, and the output signal is changed for a predetermined period from when there is a change in the internal signal. and load means for preventing abnormal current when the output signal changes when the output terminal is connected to the power supply or ground, and configured so that the output terminal can be connected to the power supply or ground. A semiconductor integrated circuit device characterized by: