JPS61103928U - - Google Patents
Info
- Publication number
- JPS61103928U JPS61103928U JP18737684U JP18737684U JPS61103928U JP S61103928 U JPS61103928 U JP S61103928U JP 18737684 U JP18737684 U JP 18737684U JP 18737684 U JP18737684 U JP 18737684U JP S61103928 U JPS61103928 U JP S61103928U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- ring oscillator
- output
- circuit
- multiphase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図はこの考案の多相パルス発生回路の一実
施例を示す回路図、第２図は第１図に示したこの
考案の多相パルス発生回路における主要な波形図
、第３図は従来のパルス発生回路の一例を示す回
路図、第４図は第３図に示した従来のパルス発生
回路における主要な波形図である。
図中、１０はリングオシレータ、１１はクロツ
ク信号整形回路、１２はカウンタ、１３は組み合
わせ回路、１４はナンドゲート、１５はラツチ回
路である。
Fig. 1 is a circuit diagram showing an embodiment of the multiphase pulse generation circuit of this invention, Fig. 2 is a main waveform diagram of the multiphase pulse generation circuit of this invention shown in Fig. 1, and Fig. 3 is a conventional circuit diagram. FIG. 4 is a circuit diagram showing an example of a pulse generating circuit shown in FIG. 4, and FIG. 4 is a diagram showing main waveforms in the conventional pulse generating circuit shown in FIG. In the figure, 10 is a ring oscillator, 11 is a clock signal shaping circuit, 12 is a counter, 13 is a combinational circuit, 14 is a NAND gate, and 15 is a latch circuit.
Claims (1)
ツチ回路と、前記ラツチ回路の出力を受けて制御
されるスタート・ストツプ型のリングオシレータ
と、前記リングオシレータの発振クロツク信号を
計数するカウンタと、前記カウンタの出力を組み
合わせて多相の信号を出力する組み合わせ回路と
からなり、前記カウンタのオーバフロー出力によ
つて前記リングオシレータの発振を停止するよう
に構成したことを特徴とする多相パルス発生回路
。 a latch circuit to which a trigger input and counter pulses are input; a start-stop ring oscillator controlled by receiving the output of the latch circuit; a counter for counting the oscillation clock signal of the ring oscillator; 1. A multiphase pulse generation circuit comprising a combination circuit that combines outputs to output a multiphase signal, and is configured to stop oscillation of the ring oscillator in response to an overflow output from the counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18737684U JPS61103928U (en) | 1984-12-12 | 1984-12-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18737684U JPS61103928U (en) | 1984-12-12 | 1984-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61103928U true JPS61103928U (en) | 1986-07-02 |
Family
ID=30744842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18737684U Pending JPS61103928U (en) | 1984-12-12 | 1984-12-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61103928U (en) |
-
1984
- 1984-12-12 JP JP18737684U patent/JPS61103928U/ja active Pending
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