JPS6330030U - - Google Patents
Info
- Publication number
- JPS6330030U JPS6330030U JP12257486U JP12257486U JPS6330030U JP S6330030 U JPS6330030 U JP S6330030U JP 12257486 U JP12257486 U JP 12257486U JP 12257486 U JP12257486 U JP 12257486U JP S6330030 U JPS6330030 U JP S6330030U
- Authority
- JP
- Japan
- Prior art keywords
- clock pulse
- phase
- clock
- frequency divider
- generates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は本願の分周回路が利用される周波数変換回
路を示す回路図、及び第３図は第１図の説明に供
するための特性図である。
１３……クロツク端子、１４及び１５……第１
及び第２アンドゲート、１６……オアゲート、１
７……第１ナンドゲート、１８……カウンタ、１
９……Ｄ―ＦＦ、２０……第２ナンドゲート、２
１……Ｔ―ＦＦ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a frequency conversion circuit in which the frequency dividing circuit of the present application is used, and FIG. 3 is for explanation of FIG. FIG. 13...Clock terminal, 14 and 15...1st
and 2nd AND gate, 16...OR gate, 1
7...First NAND gate, 18...Counter, 1
9...D-FF, 20...2nd NAND gate, 2
1...T-FF.
Claims (1)
前記クロツクパルスと同相のクロツクパルスを発
生する第１ゲート回路と、前記クロツクパルスと
逆相のクロツクパルスを発生する第２ゲート回路
と、同相又は逆相の前記クロツクパルスを計数す
る１／ｎ分周器と、該１／ｎ分周器の出力に応じ
て前記第１及び第２ゲート回路を切換制御する制
御回路とから成り、前記１／ｎ分周器が所定数計
数したことに応じて前記クロツクパルスを反転さ
せたことを特徴とする分周回路。 a clock terminal to which a clock pulse is applied;
a first gate circuit that generates a clock pulse that is in phase with the clock pulse; a second gate circuit that generates a clock pulse that is in phase with the clock pulse; and a 1/n frequency divider that counts the clock pulses that are in phase or in phase with each other; and a control circuit that switches and controls the first and second gate circuits according to the output of the 1/n frequency divider, and inverts the clock pulse in response to the 1/n frequency divider counting a predetermined number. A frequency dividing circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12257486U JPS6330030U (en) | 1986-08-09 | 1986-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12257486U JPS6330030U (en) | 1986-08-09 | 1986-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6330030U true JPS6330030U (en) | 1988-02-27 |
Family
ID=31012891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12257486U Pending JPS6330030U (en) | 1986-08-09 | 1986-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6330030U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0545443U (en) * | 1991-10-28 | 1993-06-18 | リンナイ株式会社 | Incomplete combustion detector for gas burner |
-
1986
- 1986-08-09 JP JP12257486U patent/JPS6330030U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0545443U (en) * | 1991-10-28 | 1993-06-18 | リンナイ株式会社 | Incomplete combustion detector for gas burner |
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