JPS6399277U - - Google Patents

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Publication number
JPS6399277U
JPS6399277U JP19500686U JP19500686U JPS6399277U JP S6399277 U JPS6399277 U JP S6399277U JP 19500686 U JP19500686 U JP 19500686U JP 19500686 U JP19500686 U JP 19500686U JP S6399277 U JPS6399277 U JP S6399277U
Authority
JP
Japan
Prior art keywords
circuit
generates
control circuit
pulse
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19500686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19500686U priority Critical patent/JPS6399277U/ja
Publication of JPS6399277U publication Critical patent/JPS6399277U/ja
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案によるデイジタル電圧計の構
成図、第2図はこの考案によるデイジタル電圧計
のタイミング図、第3図は従来のデイジタル電圧
計の構成図、第4図は従来のデイジタル電圧計の
タイミング図である。 図において、1は入力端子、2はのこぎり波電
圧発生回路、3は制御回路、4は比較回路、5は
ゲート制御回路、6はクロツクパルス発生回路、
7はゲート回路X、8は計数回路X、9は表示回
路、10はゲート回路Y、11は計数回路Y、1
2はデータ切替回路である。なお図中、同一また
は相当部分には同一符号を付して示してある。
Figure 1 is a configuration diagram of a digital voltmeter according to this invention, Figure 2 is a timing diagram of a digital voltmeter according to this invention, Figure 3 is a configuration diagram of a conventional digital voltmeter, and Figure 4 is a diagram of a conventional digital voltmeter. FIG. In the figure, 1 is an input terminal, 2 is a sawtooth voltage generation circuit, 3 is a control circuit, 4 is a comparison circuit, 5 is a gate control circuit, 6 is a clock pulse generation circuit,
7 is a gate circuit X, 8 is a counting circuit X, 9 is a display circuit, 10 is a gate circuit Y, 11 is a counting circuit Y, 1
2 is a data switching circuit. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力電圧に比例した計数パルスを計数するデイ
ジタル電圧計において、クロツクパルスを発生す
るクロツクパルス発生回路と、のこぎり波電圧を
発生するのこぎり波電圧発生回路と、上記入力電
圧と上記のこぎり波電圧とを比較し、両者が一致
したときストツプパルスを発生する比較回路と、
上記クロツクパルス発生回路のクロツクパルスを
入力し、上記比較器の出力の1周期ごとに通過阻
止状態を反転する2つのゲート回路と、上記2つ
のゲート回路を通過したパルスを計数する2つの
計数回路と、上記2つのゲート回路の通過阻止状
態を常に相補的に制御するゲート制御回路と、上
記ゲート制御回路の出力により上記2つの計数回
路の計数値を適宜切替えて出力する切替回路と、
上記切替回路により上記2つの計数回路のうち、
計数を完了した方の計数値を表示する表示回路と
、上記のこぎり波電圧発生回路の動作タイミング
のスタートパルスを発生するとともに上記ゲート
制御回路の出力に基づいて上記2つの計数回路の
計数値を零にリセツトするパルスを発生し、かつ
上記表示回路の表示値を更新するパルスを発生す
る制御回路とを具備したことを特徴とするデイジ
タル電圧計。
In a digital voltmeter that counts pulses proportional to an input voltage, a clock pulse generation circuit that generates clock pulses, a sawtooth voltage generation circuit that generates a sawtooth voltage, and a comparison between the input voltage and the sawtooth voltage, a comparison circuit that generates a stop pulse when the two match;
two gate circuits that input the clock pulses of the clock pulse generation circuit and invert the pass blocking state every cycle of the output of the comparator; and two counting circuits that count the pulses that have passed through the two gate circuits; a gate control circuit that always complementarily controls the passage blocking state of the two gate circuits, and a switching circuit that appropriately switches and outputs the count values of the two counting circuits based on the output of the gate control circuit;
Of the two counting circuits, the switching circuit allows
A display circuit that displays the count value of the one that has completed counting, and a start pulse for the operation timing of the sawtooth voltage generation circuit, and also zeros the count values of the two counting circuits based on the output of the gate control circuit. 1. A digital voltmeter comprising: a control circuit that generates a pulse that resets the value of the display circuit; and a control circuit that generates a pulse that updates the display value of the display circuit.
JP19500686U 1986-12-18 1986-12-18 Pending JPS6399277U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19500686U JPS6399277U (en) 1986-12-18 1986-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19500686U JPS6399277U (en) 1986-12-18 1986-12-18

Publications (1)

Publication Number Publication Date
JPS6399277U true JPS6399277U (en) 1988-06-27

Family

ID=31152497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19500686U Pending JPS6399277U (en) 1986-12-18 1986-12-18

Country Status (1)

Country Link
JP (1) JPS6399277U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017040580A (en) * 2015-08-20 2017-02-23 株式会社オートネットワーク技術研究所 Current sensing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017040580A (en) * 2015-08-20 2017-02-23 株式会社オートネットワーク技術研究所 Current sensing circuit

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