JPH0461934U - - Google Patents
Info
- Publication number
- JPH0461934U JPH0461934U JP10516990U JP10516990U JPH0461934U JP H0461934 U JPH0461934 U JP H0461934U JP 10516990 U JP10516990 U JP 10516990U JP 10516990 U JP10516990 U JP 10516990U JP H0461934 U JPH0461934 U JP H0461934U
- Authority
- JP
- Japan
- Prior art keywords
- digital data
- input
- outputs
- converter
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例によるＡ／Ｄ変換装
置を適用した補正データ発生器の構成を示すブロ
ツク図、第２図は同補正データ発生器におけるポ
テンシヨメータからのアナログ電圧がＶ０からＶ
１へ変わつた時の動作を示すタイミングチヤート
、第３図は同補正データ発生器におけるＡ／Ｄコ
ンバータの出力にふらつきが生じている場合の動
作を示すタイミングチヤート、第４図は、従来の
テレビジヨンカメラの補正データ発生器の概略ブ
ロツク図である。
主要部分の符号の説明、１……ポテンシヨメー
タ、２……Ａ／Ｄコンバータ、３……ラツチ回路
、４……デジタルコンパレータ、５……ＲＯＭ、
６……カウンタ、７……Ｄ／Ａコンバータ。
FIG. 1 is a block diagram showing the configuration of a correction data generator to which an A/D converter according to an embodiment of the present invention is applied, and FIG. 2 shows that the analog voltage from the potentiometer in the correction data generator is V0. from V
1. Figure 3 is a timing chart showing the operation when the output of the A/D converter in the correction data generator fluctuates. Figure 4 is a timing chart showing the operation when the output changes to 1. FIG. 2 is a schematic block diagram of a correction data generator of a camera; Explanation of symbols of main parts, 1... Potentiometer, 2... A/D converter, 3... Latch circuit, 4... Digital comparator, 5... ROM,
6...Counter, 7...D/A converter.
Claims (1)
第１のデジタルデータを出力するＡ／Ｄコンバー
タと、 前記第１のデジタルデータを入力し、ラツチ信
号を入力したとき、直前に入力された第１のデジ
タルデータと同一の値である第２のデジタルデー
タを出力し、該第２のデジタルデータの出力を保
持するラツチ回路と、 前記Ａ／Ｄコンバータから出力された第１のデ
ジタルデータと前記ラツチ回路から出力された第
２のデジタルデータを入力して該第１のデジタル
データと該第２のデジタルデータとが同一の値か
否かを示す状態信号を出力する比較回路と、 前記比較回路からの状態信号を入力し、前記比
較回路で比較された２つのデジタルデータが同一
でないとき、一定時間後に前記ラツチ回路に前記
ラツチ信号を出力するタイマ回路と、 を備えたことを特徴とするＡ／Ｄ変換装置。[Scope of claim for utility model registration] Input an analog signal and convert it to a digital quantity,
an A/D converter that outputs first digital data; and when the first digital data is input and a latch signal is input, a second A/D converter that has the same value as the first digital data input immediately before is input. a latch circuit that outputs digital data and holds the output of the second digital data; and inputs the first digital data output from the A/D converter and the second digital data output from the latch circuit. a comparison circuit that outputs a status signal indicating whether or not the first digital data and the second digital data have the same value; and a status signal from the comparison circuit is input and the comparison circuit compares the An A/D conversion device comprising: a timer circuit that outputs the latch signal to the latch circuit after a certain period of time when the two digital data obtained are not the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10516990U JPH0461934U (en) | 1990-10-05 | 1990-10-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10516990U JPH0461934U (en) | 1990-10-05 | 1990-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0461934U true JPH0461934U (en) | 1992-05-27 |
Family
ID=31850762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10516990U Pending JPH0461934U (en) | 1990-10-05 | 1990-10-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0461934U (en) |
-
1990
- 1990-10-05 JP JP10516990U patent/JPH0461934U/ja active Pending
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