JPH02118334U

JPH02118334U -

Info

Publication number: JPH02118334U
Application number: JP2757389U
Authority: JP
Priority date: 1989-03-10
Filing date: 1989-03-10
Publication date: 1990-09-21

Description

[Brief explanation of drawings]

第１図及び第２図は本考案の一実施例を示し、
第１図はＡ／Ｄコンバータのブロツク図、第２図
は動作解説グラフであり、第３図及び第４図は従
来例を示し、第３図は比較形Ａ／Ｄコンバータの
ブロツク図、第４図は積分形Ａ／Ｄコンバータの
ブロツク図である。４…入力電圧、６…コンパレータ、８…ロジツ
ク回路、１１…クロツクジエネレータ、１３…Ａ
／Ｄコンバータ、２４…三角波発生器、２７…ク
ロツクパルス、２８…三角波。 1 and 2 show an embodiment of the present invention,
Fig. 1 is a block diagram of an A/D converter, Fig. 2 is a graph explaining the operation, Figs. 3 and 4 show a conventional example, Fig. 3 is a block diagram of a comparative A/D converter, and Fig. FIG. 4 is a block diagram of an integral type A/D converter. 4...Input voltage, 6...Comparator, 8...Logic circuit, 11...Clock generator, 13...A
/D converter, 24... triangular wave generator, 27... clock pulse, 28... triangular wave.

Claims

[Scope of utility model registration request]

A logic circuit is connected to the output terminal of the comparator, and a triangular wave generator whose operation is controlled by the logic circuit and has a predetermined time constant is connected to one input terminal of the comparator, and a clock pulse generated by the clock generator is connected to the output terminal of the comparator. , from the time when the triangular wave generator starts generating a triangular wave until the triangular wave matches the input voltage to the other input terminal of the comparator, and converts the input voltage into a digital value according to the number of clock pulses. An A/D converter characterized in that it is configured as follows.