JPS6384631U - - Google Patents
Info
- Publication number
- JPS6384631U JPS6384631U JP17772186U JP17772186U JPS6384631U JP S6384631 U JPS6384631 U JP S6384631U JP 17772186 U JP17772186 U JP 17772186U JP 17772186 U JP17772186 U JP 17772186U JP S6384631 U JPS6384631 U JP S6384631U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- circuit
- capacitor
- voltage
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図の動作を示すタイミング図、第３図ａ及
びｂはスイツチング回路の他の例を示す回路図で
ある。
１…発振回路、２，３…インバータ、４…分周
回路、５…スイツチング回路、６…コンデンサ、
７…インバータ、８…ダイオード。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of FIG. 1, and FIGS. 3a and 3b are circuit diagrams showing other examples of the switching circuit. 1... Oscillation circuit, 2, 3... Inverter, 4... Frequency dividing circuit, 5... Switching circuit, 6... Capacitor,
7...Inverter, 8...Diode.
Claims (1)
スされた後発振を開始する発振回路と、前記出力
端子に接続され前記所定電圧Ｖｂと異なるスレツ
シヨルド電圧Ｖｔａを有するインバータと、前記
発振回路の発振出力を分周する分周回路と、前記
インバータと分周回路の分周出力を入力するスイ
ツチング手段と、該スイツチング手段と直列接続
されたコンデンサと、該コンデンサの端子電圧を
入力するパルス発生手段とを備え、発振開始後前
記パルス発生手段が前記コンデンサの端子電圧が
所定値になつたことを検出するまでの期間をリセ
ツトパルスとすることを特徴とするリセツトパル
ス発生回路。 an oscillation circuit that starts oscillation after an output terminal is biased to a predetermined voltage Vb when power is applied; an inverter connected to the output terminal and having a threshold voltage Vta different from the predetermined voltage Vb; and an oscillation circuit that divides the oscillation output of the oscillation circuit. a frequency divider circuit that rotates, a switching means that inputs the divided outputs of the inverter and the frequency divider circuit, a capacitor connected in series with the switching means, and a pulse generation means that inputs the terminal voltage of the capacitor, A reset pulse generating circuit characterized in that a period after the start of oscillation until the pulse generating means detects that the terminal voltage of the capacitor has reached a predetermined value is used as a reset pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17772186U JPS6384631U (en) | 1986-11-19 | 1986-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17772186U JPS6384631U (en) | 1986-11-19 | 1986-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6384631U true JPS6384631U (en) | 1988-06-03 |
Family
ID=31119191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17772186U Pending JPS6384631U (en) | 1986-11-19 | 1986-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384631U (en) |
-
1986
- 1986-11-19 JP JP17772186U patent/JPS6384631U/ja active Pending