JPS61166627U - - Google Patents
Info
- Publication number
- JPS61166627U JPS61166627U JP4917185U JP4917185U JPS61166627U JP S61166627 U JPS61166627 U JP S61166627U JP 4917185 U JP4917185 U JP 4917185U JP 4917185 U JP4917185 U JP 4917185U JP S61166627 U JPS61166627 U JP S61166627U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- cmos inverter
- supply terminal
- terminal
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Dc-Dc Converters (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Description
第１図および第２図はそれぞれ本考案の倍電圧
パルス発生回路の一実施例の回路図および波形図
、第３図は本考案の他の実施例の回路図、第４図
は従来の倍電圧パルス発生回路の回路図である。
１……直流電源、２，１６，１８……ＣＭＯＳ
インバータ、３……ＶＤＤ端子、４……出力端子
、５……ダイオード、６……コンデンサ、７……
端子、８……負荷端子、９……バイポーラトラン
ジスタ、１０……抵抗、１１……ダイオード、１
２……ＶＳＳ端子、１３……トランジスタ、１４
……入力端子、１５……抵抗、１７……ＣＭＯＳ
・ＩＣ。
Figures 1 and 2 are a circuit diagram and waveform diagram of an embodiment of the voltage doubler pulse generator of the present invention, Figure 3 is a circuit diagram of another embodiment of the present invention, and Figure 4 is a circuit diagram of a conventional doubler voltage pulse generator. FIG. 2 is a circuit diagram of a voltage pulse generation circuit. 1...DC power supply, 2, 16, 18...CMOS
Inverter, 3...VDD terminal, 4...Output terminal, 5...Diode, 6...Capacitor, 7...
Terminal, 8... Load terminal, 9... Bipolar transistor, 10... Resistor, 11... Diode, 1
2...VSS terminal, 13...Transistor, 14
...Input terminal, 15...Resistor, 17...CMOS
・IC.
Claims (1)
タと、この第１のＣＭＯＳインバータの第１の電
源端子と出力端子の間に直列に接続されたダイオ
ードおよびコンデンサと、このダイオードおよび
コンデンサの接続点に第１の電源端子が接続され
前記第１のＣＭＯＳインバータの第２の電源端子
に第２の電源端子が接続された第２のＣＭＯＳイ
ンバータとを含み、前記第１および第２のＢＭＯ
Ｓインバータそれぞれの入力端子に同期した入力
信号を入力し、前記第２のＣＭＯＳインバータの
出力端子と前記第２の電源端子との間に出力を得
ることを特徴とする倍電圧パルス発生回路。 A first CMOS inverter connected to a DC power supply, a diode and a capacitor connected in series between the first power supply terminal and the output terminal of the first CMOS inverter, and a first CMOS inverter connected to the connection point of the diode and the capacitor. a second CMOS inverter having one power supply terminal connected to the first power supply terminal and a second power supply terminal connected to a second power supply terminal of the first CMOS inverter;
A voltage doubler pulse generation circuit, characterized in that a synchronized input signal is input to each input terminal of the S inverter, and an output is obtained between the output terminal of the second CMOS inverter and the second power supply terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4917185U JPS61166627U (en) | 1985-04-02 | 1985-04-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4917185U JPS61166627U (en) | 1985-04-02 | 1985-04-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61166627U true JPS61166627U (en) | 1986-10-16 |
Family
ID=30566117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4917185U Pending JPS61166627U (en) | 1985-04-02 | 1985-04-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61166627U (en) |
-
1985
- 1985-04-02 JP JP4917185U patent/JPS61166627U/ja active Pending