JPS6372937U - - Google Patents
Info
- Publication number
- JPS6372937U JPS6372937U JP16671886U JP16671886U JPS6372937U JP S6372937 U JPS6372937 U JP S6372937U JP 16671886 U JP16671886 U JP 16671886U JP 16671886 U JP16671886 U JP 16671886U JP S6372937 U JPS6372937 U JP S6372937U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- pulse
- phase comparator
- lag
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Description
第1図は、この考案の位相比較器の第一実施例
を示す回路図、第2図は、この考案の位相比較器
と共に用いて好適なタイミング抽出回路を示す図
、第3図A〜Gは、この考案の第一実施例の位相
比較器の動作説明に供するタイミングチヤート、
第4図は、この考案の位相比較器の第二実施例を
示す回路図、第5図は、この考案の位相比較器の
第三実施例を示す回路図、第6図は、この考案の
位相比較器の第三実施例を示す回路図である。
11,13…位相比較器の入力端子、20…パ
ルス発生回路、21,23…論理積回路、25…
インバータ、40…制御信号発生回路、41…第
一スイツチ素子、43…第二スイツチ素子、51
…第一抵坑器、53…第二抵抗器、55…抵抗器
、57…コンデンサ、61…出力端子、101…
コンデンサ、103…演算増幅器。
FIG. 1 is a circuit diagram showing a first embodiment of the phase comparator of this invention, FIG. 2 is a diagram showing a timing extraction circuit suitable for use with the phase comparator of this invention, and FIGS. 3 A to G is a timing chart for explaining the operation of the phase comparator of the first embodiment of this invention,
Fig. 4 is a circuit diagram showing a second embodiment of the phase comparator of this invention, Fig. 5 is a circuit diagram showing a third embodiment of the phase comparator of this invention, and Fig. 6 is a circuit diagram showing a third embodiment of the phase comparator of this invention. FIG. 3 is a circuit diagram showing a third embodiment of a phase comparator. 11, 13... Input terminal of phase comparator, 20... Pulse generation circuit, 21, 23... AND circuit, 25...
Inverter, 40... Control signal generation circuit, 41... First switch element, 43... Second switch element, 51
...first resistor, 53...second resistor, 55...resistor, 57...capacitor, 61...output terminal, 101...
Capacitor, 103... operational amplifier.
Claims (1)
はバースト状のデイジタル信号とから制御信号を
出力するための位相比較器において、 デイジタル信号に対する出力信号の位相の進み
及び遅れを表わす進みパルス及び遅れパルスを発
生するパルス発生回路と、 第一及び第二基準電圧点間に設けられ前記進み
パルス及び遅れパルスに対応して電圧レベルが変
動される制御信号を出力する制御信号出力回路と
を具えたことを特徴とする位相比較器。 (2) 前記制御信号出力回路は、前記第一基準電
圧点に一方の端子が接続され前記進みパルスによ
つてオン・オフされる第一スイツチ素子及び前記
第二基準電圧点に一方の端子が接続され前記遅れ
パルスによつてオン・オフされる第二スイツチ素
子の直列回路と、 前記第一及び第二スイツチ素子の接続点に接続
され制御信号を出力する積分回路と を具えることを特徴とする実用新案登録請求の範
囲第1項記載の位相比較器。[Claims for Utility Model Registration] (1) In a phase comparator for outputting a control signal from an output signal from a voltage controlled oscillator and a continuous or burst digital signal, the phase lead of the output signal with respect to the digital signal. and a pulse generation circuit that generates lead pulses and lag pulses representing lag, and a control signal that is provided between the first and second reference voltage points and whose voltage level is varied in response to the lead pulse and lag pulse. A phase comparator comprising a control signal output circuit. (2) The control signal output circuit includes a first switch element having one terminal connected to the first reference voltage point and turned on and off by the advance pulse, and one terminal connected to the second reference voltage point. A series circuit of second switch elements connected to each other and turned on and off by the delayed pulse, and an integrating circuit connected to a connection point of the first and second switch elements and outputting a control signal. A phase comparator according to claim 1 of the utility model registration claim.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16671886U JPS6372937U (en) | 1986-10-31 | 1986-10-31 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16671886U JPS6372937U (en) | 1986-10-31 | 1986-10-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6372937U true JPS6372937U (en) | 1988-05-16 |
Family
ID=31097964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16671886U Pending JPS6372937U (en) | 1986-10-31 | 1986-10-31 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6372937U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006254401A (en) * | 2005-02-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Delay locked loop circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5619769A (en) * | 1979-07-26 | 1981-02-24 | Ricoh Co Ltd | Ink-jet recording device |
JPS57186838A (en) * | 1981-05-14 | 1982-11-17 | Nec Corp | Clock signal reproducing circuit |
JPS6036908U (en) * | 1983-08-19 | 1985-03-14 | 森田工業株式会社 | dust collection can |
-
1986
- 1986-10-31 JP JP16671886U patent/JPS6372937U/ja active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5619769A (en) * | 1979-07-26 | 1981-02-24 | Ricoh Co Ltd | Ink-jet recording device |
JPS57186838A (en) * | 1981-05-14 | 1982-11-17 | Nec Corp | Clock signal reproducing circuit |
JPS6036908U (en) * | 1983-08-19 | 1985-03-14 | 森田工業株式会社 | dust collection can |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006254401A (en) * | 2005-02-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Delay locked loop circuit |