JPH0213373U - - Google Patents

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Publication number
JPH0213373U
JPH0213373U JP8995088U JP8995088U JPH0213373U JP H0213373 U JPH0213373 U JP H0213373U JP 8995088 U JP8995088 U JP 8995088U JP 8995088 U JP8995088 U JP 8995088U JP H0213373 U JPH0213373 U JP H0213373U
Authority
JP
Japan
Prior art keywords
trigger signal
synchronization signal
monostable multivibrator
output
composite synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8995088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8995088U priority Critical patent/JPH0213373U/ja
Publication of JPH0213373U publication Critical patent/JPH0213373U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る周波数自動判別回路の一
実施例を示す回路図、第2図は第1図の実施例を
説明するためのタイミングチヤート、第3図は従
来の周波数自動判別回路を示す回路図、第4図は
第3図の動作を説明するためのタイミングチヤー
トである。 1…入力端子、2…単安定マルチバイブレータ
、3…積分回路、4…増幅回路、5…周波数/電
圧変換回路、Q1,Q2…トランジスタ、R4…
抵抗、C2…コンデンサ。
Fig. 1 is a circuit diagram showing an embodiment of an automatic frequency discrimination circuit according to the present invention, Fig. 2 is a timing chart for explaining the embodiment of Fig. 1, and Fig. 3 is a circuit diagram showing a conventional automatic frequency discrimination circuit. The circuit diagram shown in FIG. 4 is a timing chart for explaining the operation of FIG. 3. 1... Input terminal, 2... Monostable multivibrator, 3... Integrating circuit, 4... Amplifying circuit, 5... Frequency/voltage conversion circuit, Q1, Q2... Transistor, R4...
Resistor, C2...capacitor.

Claims (1)

【実用新案登録請求の範囲】 複合同期信号を導入し、この複合同期信号に基
づいてトリガ信号を発生するトリガ信号発生手段
と、 前記複合同期信号の垂直同期信号期間に前記ト
リガ信号の発生を遮断する制御手段と、 前記トリガ信号発生手段からのトリガ信号によ
つて一定パルス幅のパルスを出力する単安定マル
チバイブレータと、 この単安定マルチバイブレータの出力を積分し
て平均化し周波数判別出力を出力する積分回路と
を具備したことを特徴とする周波数自動判別回路
[Claims for Utility Model Registration] Trigger signal generating means for introducing a composite synchronization signal and generating a trigger signal based on the composite synchronization signal, and blocking generation of the trigger signal during a vertical synchronization signal period of the composite synchronization signal. a monostable multivibrator that outputs a pulse with a constant pulse width in response to a trigger signal from the trigger signal generation means, and a monostable multivibrator that integrates and averages the output of the monostable multivibrator to output a frequency discrimination output. An automatic frequency discrimination circuit characterized by comprising an integrating circuit.
JP8995088U 1988-07-08 1988-07-08 Pending JPH0213373U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8995088U JPH0213373U (en) 1988-07-08 1988-07-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8995088U JPH0213373U (en) 1988-07-08 1988-07-08

Publications (1)

Publication Number Publication Date
JPH0213373U true JPH0213373U (en) 1990-01-26

Family

ID=31314488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8995088U Pending JPH0213373U (en) 1988-07-08 1988-07-08

Country Status (1)

Country Link
JP (1) JPH0213373U (en)

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