JPH0320399U - - Google Patents
Info
- Publication number
- JPH0320399U JPH0320399U JP8013489U JP8013489U JPH0320399U JP H0320399 U JPH0320399 U JP H0320399U JP 8013489 U JP8013489 U JP 8013489U JP 8013489 U JP8013489 U JP 8013489U JP H0320399 U JPH0320399 U JP H0320399U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- output
- frequency divider
- signal
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Description
第１図は本考案に係るブザー駆動回路の一実施
例を示す構造図、第２図は動作説明用のタイムチ
ヤート、第３図は従来のブザー駆動回路である。
１……クロツク発生回路、２……分周器、３…
…単安定マルチバイブレータ、４……第１のパル
ス発生回路、５……第２のパルス発生回路、６…
…ＲＳフリツプフロツプ、７……ブザー。
FIG. 1 is a structural diagram showing one embodiment of a buzzer drive circuit according to the present invention, FIG. 2 is a time chart for explaining the operation, and FIG. 3 is a conventional buzzer drive circuit. 1... Clock generation circuit, 2... Frequency divider, 3...
... Monostable multivibrator, 4... First pulse generating circuit, 5... Second pulse generating circuit, 6...
...RS flip-flop, 7...buzzer.
Claims (1)
安定マルチバイブレータと、 前記トリガ信号発生時を検出し、一定幅のパル
スを出力する第１のパルス発生回路と、 前記単安定マルチバイブレータの出力パルスの
後縁を検出し、一定幅のパルスを出力する第２の
パルス発生回路と、 前記第１のパルス発生回路の出力パルスでセツ
トされ、前記第２のパルス発生回路の出力パルス
でリセツトされるＲＳフリツプフロツプと、 基準クロツクを分周することによりブザーを鳴
動するためのパルス信号を送出するが、前記ＲＳ
フリツプフロツプよりクリア信号が与えられたと
きはパルス出力を停止するように構成された分周
器 を具備し、前記ＲＳフリツプフロツプの出力を
前記分周器のクリア信号とし、トリガ信号が入力
された後単安定マルチバイブレータの出力パルス
の後縁のまでの期間に限り、分周器からクロツク
信号が出力されるようにしたことを特徴とするブ
ザー駆動回路。[Claims for Utility Model Registration] A monostable multivibrator that outputs a pulse of a constant width in response to a trigger signal; a first pulse generation circuit that detects when the trigger signal is generated and outputs a pulse of a constant width; a second pulse generation circuit that detects the trailing edge of the output pulse of the stable multivibrator and outputs a pulse of a constant width; The RS flip-flop is reset by the output pulse, and the reference clock is frequency-divided to send out a pulse signal to sound the buzzer.
A frequency divider configured to stop pulse output when a clear signal is applied from the flip-flop is provided, and the output of the RS flip-flop is used as the clear signal of the frequency divider, and after a trigger signal is input, the frequency divider is configured to stop pulse output. A buzzer drive circuit characterized in that a clock signal is output from a frequency divider only during a period up to the trailing edge of an output pulse of a stable multivibrator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8013489U JPH0320399U (en) | 1989-07-10 | 1989-07-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8013489U JPH0320399U (en) | 1989-07-10 | 1989-07-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320399U true JPH0320399U (en) | 1991-02-27 |
Family
ID=31624919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8013489U Pending JPH0320399U (en) | 1989-07-10 | 1989-07-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320399U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100717585B1 (en) * | 2006-02-09 | 2007-05-15 | 양옥현 | Coat hanger that have flexible arm rest |
-
1989
- 1989-07-10 JP JP8013489U patent/JPH0320399U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100717585B1 (en) * | 2006-02-09 | 2007-05-15 | 양옥현 | Coat hanger that have flexible arm rest |