JPH0373037U

JPH0373037U -

Info

Publication number: JPH0373037U
Application number: JP13461589U
Authority: JP
Priority date: 1989-11-20
Filing date: 1989-11-20
Publication date: 1991-07-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、第２
図Ａ〜Ｇは第１図の各点に於ける波形図、第３図
は従来例を示す回路図、第４図Ａ〜Ｇは第３図の
各点に於ける波形図である。２……タイマースタートスイツチ、３……トリ
ガパルス発生回路、４……Ｄフリツプ・フロツプ
回路、６……タイマー回路、７，８……第１第２
のＮＯＲゲート回路、９……音声発生回路、Ｂ，
Ａ……Ｄフリツプ・フロツプ回路の第１第２の出
力端子、Ｂ′，Ｃ……第１ＮＯＲゲート回路の第
１第２入力端子、Ｄ_１……ダイオード、Ｒ_４……
抵抗。 Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figures A to G are waveform diagrams at each point in Figure 1, Figure 3 is a circuit diagram showing a conventional example, and Figures A to G are waveform diagrams at each point in Figure 3. 2... Timer start switch, 3... Trigger pulse generation circuit, 4... D flip-flop circuit, 6... Timer circuit, 7, 8... First second
NOR gate circuit, 9...sound generation circuit, B,
A...D first and second output terminals of the flip-flop circuit, B', C...first and second input terminals of the first NOR gate circuit, _D1 ...diode, _R4 ...
resistance.

Claims

[Claims for Utility Model Registration] (1) A timer start switch, a trigger pulse generation circuit, a flip-flop circuit to which pulses from the trigger pulse generation circuit are applied, and an operation using the output of the flip-flop circuit. It consists of a timer circuit that is controlled to be in the state or stop state, and an audio generation circuit that generates an audio signal for a certain period of time at a predetermined time interval using a signal from the timer circuit, and a predetermined output terminal of the flip-flop circuit and the timer circuit. A timer control circuit characterized in that a circuit means is provided between a predetermined input terminal of the circuit for forcibly setting the timer circuit to an initial state when the timer start switch is operated to start the timer. . (2) the flip-flop circuit is a D flip-flop circuit, and the timer circuit includes a first NOR gate circuit whose first input terminal is connected to a first output terminal of the D flip-flop circuit; Registration of a utility model characterized by comprising a second NOR gate circuit that inverts the output of the first NOR gate, and a resistor and a capacitor connected between the input and output of the second NOR gate circuit. A timer control circuit according to claim 1. (3) The circuit means for forcibly setting the timer circuit to the initial state includes the second input terminal of the first NOR gate circuit constituting the timer circuit and the second output terminal of the D flip-flop circuit. 2. The timer control circuit according to claim 2, wherein the timer control circuit is comprised of a resistor and a diode connected between.