JPS6437901U - - Google Patents
Info
- Publication number
- JPS6437901U JPS6437901U JP13315787U JP13315787U JPS6437901U JP S6437901 U JPS6437901 U JP S6437901U JP 13315787 U JP13315787 U JP 13315787U JP 13315787 U JP13315787 U JP 13315787U JP S6437901 U JPS6437901 U JP S6437901U
- Authority
- JP
- Japan
- Prior art keywords
- recording
- flop
- flip
- control signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Description
第１図は本考案の実施例に係わるテープレコー
ダの記録遅延回路を示すブロツク図、第２図は第
１図の各部の状態を示す電圧波形図、第３図及び
第４図は遅延出力回路の変形例をそれぞれ示すブ
ロツク図、第５図はカウンタ入力制御回路の変形
例を示すブロツク図、第６図は第５図の各部の電
圧波形図である。
１……テープ、２……消去ヘツド、３……記録
ヘツド、９……記録制御信号入力端子、１２……
クロツクパルス供給端子、１３……プログラマブ
ルカウンタ、１４……フリツプフロツプ、１５…
…トリガ回路、１６……カウンタ入力制御回路、
１７……遅延出力回路、２１……排他的ＯＲゲー
ト。
Fig. 1 is a block diagram showing a recording delay circuit of a tape recorder according to an embodiment of the present invention, Fig. 2 is a voltage waveform diagram showing the states of each part in Fig. 1, and Figs. 3 and 4 are delay output circuits. FIG. 5 is a block diagram showing a modification of the counter input control circuit, and FIG. 6 is a voltage waveform diagram of each part in FIG. 1... Tape, 2... Erasing head, 3... Recording head, 9... Recording control signal input terminal, 12...
Clock pulse supply terminal, 13...Programmable counter, 14...Flip-flop, 15...
...Trigger circuit, 16...Counter input control circuit,
17... Delay output circuit, 21... Exclusive OR gate.
Claims (1)
御信号が供給される記録制御信号入力端子９と、 テープの走行速度に対応した周波数のクロツク
パルスが供給されるクロツクパルス入力端子１２
と、 クロツク入力端子と出力端子とを有し、前記ク
ロツク入力端子が前記クロツクパルス入力端子１
２に接続され、所定数のクロツクパルスが入力し
た時に出力パルスを前記出力端子に発生するカウ
ンタ１３と、 前記記録制御信号入力端子９に接続され、前記
記録制御信号の記録指令状態を示す波形の前縁時
点と後縁時点でそれぞれトリガパルスを発生する
トリガ回路１５と、 前記トリガ回路１５から供給される前記トリガ
パルスに応答してセツト状態となり、前記カウン
タ１３の前記出力端子から得られる出力パルスに
応答してリセツト状態になるフリツプフロツプ１
４と、 前記フリツプフロツプ１４の出力に応答して前
記フリツプフロツプ１４のセツト期間にほぼ対応
する期間に前記カウンタ１３の前記クロツク入力
端子に前記クロツクパルスを与えるカウンタ入力
制御回路１６と、 前記記録制御信号入力端子９と前記フリツプフ
ロツプ１４の出力端子とに接続され、前記記録制
御信号が記録指令状態にあると共に前記フリツプ
フロツプ１４がセツト状態にある時及び前記記録
制御信号が記録非指令状態にあると共に前記フリ
ツプフロツプ１４がリセツト状態にある時には記
録を指令しない出力を発生し、前記記録制御信号
が記録指令状態にあると共に前記フリツプフロツ
プ１４がリセツト状態にある時及び前記記録制御
信号が記録非指令状態にあると共に前記フリツプ
フロツプ１４がセツト状態にある時に記録を指令
する出力を発生する記録制御信号遅延出力回路１
７と から成るテープレコーダの記録遅延回路。[Claims for Utility Model Registration] A recording control signal input terminal 9 to which a recording control signal for setting the tape recorder to a recording state is supplied, and a clock pulse input terminal 12 to which a clock pulse having a frequency corresponding to the running speed of the tape is supplied.
and a clock input terminal and an output terminal, the clock input terminal being connected to the clock pulse input terminal 1.
2, which generates an output pulse at the output terminal when a predetermined number of clock pulses are input; a trigger circuit 15 that generates a trigger pulse at the edge time and a trailing edge time, respectively; and a set state in response to the trigger pulse supplied from the trigger circuit 15, and an output pulse obtained from the output terminal of the counter 13; Flip-flop 1 responds to reset state
4, a counter input control circuit 16 for applying the clock pulse to the clock input terminal of the counter 13 during a period substantially corresponding to the set period of the flip-flop 14 in response to the output of the flip-flop 14; and the recording control signal input terminal. 9 and the output terminal of the flip-flop 14, when the recording control signal is in the recording command state and the flip-flop 14 is in the set state, and when the recording control signal is in the recording non-command state and the flip-flop 14 is in the set state. When in the reset state, it generates an output that does not command recording, and when the recording control signal is in the recording command state and the flip-flop 14 is in the reset state, and when the recording control signal is in the recording non-command state and the flip-flop 14 Recording control signal delay output circuit 1 that generates an output commanding recording when is in the set state.
A tape recorder recording delay circuit consisting of 7 and .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13315787U JPH0514324Y2 (en) | 1987-08-31 | 1987-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13315787U JPH0514324Y2 (en) | 1987-08-31 | 1987-08-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6437901U true JPS6437901U (en) | 1989-03-07 |
| JPH0514324Y2 JPH0514324Y2 (en) | 1993-04-16 |
Family
ID=31390772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13315787U Expired - Lifetime JPH0514324Y2 (en) | 1987-08-31 | 1987-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514324Y2 (en) |
-
1987
- 1987-08-31 JP JP13315787U patent/JPH0514324Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0514324Y2 (en) | 1993-04-16 |
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