JPS6118657U

JPS6118657U - Analog signal momentary interruption generation circuit

Info

Publication number: JPS6118657U
Application number: JP1984102160U
Authority: JP
Inventors: 武雄内野
Original assignee: 日本電気株式会社
Priority date: 1984-07-06
Filing date: 1984-07-06
Publication date: 1986-02-03

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案実施例アナログ信号瞬断発生回路のブ爾
ツク構成図。第２図は周期発生回路の一例を示すブ爾ツク構成図。第３図は正弦波信号の瞬断波形を示す図。第４図は従来の正弦波信号の瞬断波形を示す図。ゝ″１・・・入力端子、２・・・遅延設定端子、３
・・・瞬断タイムスロット数設定端子、４・・・クロッ
ク検出回路、５・一・遅延回路、６・・・周期発生回路
、７・・・アナログスイッチ、８・・・記憶用コンデン
サ、９・・・緩衝増幅器、１０・・・出力端子。FIG. 1 is a block diagram of an analog signal instantaneous interruption generating circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing an example of a period generating circuit. FIG. 3 is a diagram showing a momentary interruption waveform of a sine wave signal. FIG. 4 is a diagram showing an instantaneous interruption waveform of a conventional sine wave signal.ゝ″1...Input terminal, 2...Delay setting terminal, 3
...Momentary interruption time slot number setting terminal, 4...Clock detection circuit, 5.1 delay circuit, 6.Period generation circuit, 7.Analog switch, 8.Storage capacitor, 9 ... Buffer amplifier, 10... Output terminal.

Claims

[Claim for Utility Model Registration] An input terminal to which an analog input signal is connected, an analog switch that connects the signal of this input terminal, a slow-south amplifier through which the output of this analog switch passes, and an output of this buffer amplifier that In the analog signal instantaneous interruption generation circuit, which includes a connected output terminal 7 and a control circuit that controls the on/off of the analog switch, the control circuit includes a clock detection circuit that detects the period of the signal at the input terminal. , a delay circuit that delays the output of this clock detection circuit according to a value detected externally; and a delay circuit that turns off the analog switch during a period when the number of output pulses of this delay circuit specified from the outside has elapsed. 1. An analog signal instantaneous interruption generating circuit, comprising circuit means for generating a control signal, and a voltage holding circuit provided at the input of the buffer amplifier.