JPS60113572U - Data setting device - Google Patents
Data setting deviceInfo
- Publication number
- JPS60113572U JPS60113572U JP110084U JP110084U JPS60113572U JP S60113572 U JPS60113572 U JP S60113572U JP 110084 U JP110084 U JP 110084U JP 110084 U JP110084 U JP 110084U JP S60113572 U JPS60113572 U JP S60113572U
- Authority
- JP
- Japan
- Prior art keywords
- data
- setting device
- register
- shift circuit
- data setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Small-Scale Networks (AREA)
- Communication Control (AREA)
- Radar Systems Or Details Thereof (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ設定装置の構成を示す図、第２図
は本考案によるデータ設定装置の構成を示す図、第３図
は本考案によるデータ設定装置１は入力直列データ、２
はクロ、ツク、３はデータシフト回路八、４はデータシ
フト回路Ｂ、５はデータレジスタ、６はアドレスレジス
タ、７はコンパレータ、８はアドレスデータ１．９はア
ドレ −ス、１０は…制御データ、１１は設定デ
ータ、１２は出力直列データ、１３はアドレス一致信号
、”１４はバイト設定信号、１５はパルス発生回路、１
′６はデータ設定パルス、１７．１８はインバータ
、１９はバイトパルスである。なお、図中、同一あるい
は相当部分には同一符号を付して示して−ある。
第２図FIG. 1 is a diagram showing the configuration of a conventional data setting device, FIG. 2 is a diagram showing the configuration of a data setting device according to the present invention, and FIG. 3 is a diagram showing the configuration of a data setting device 1 according to the present invention.
3 is data shift circuit 8, 4 is data shift circuit B, 5 is data register, 6 is address register, 7 is comparator, 8 is address data 1.9 is address, 10 is... control data , 11 is setting data, 12 is output serial data, 13 is address match signal, 14 is byte setting signal, 15 is pulse generation circuit, 1
'6 is a data setting pulse, 17.18 is an inverter, and 19 is a byte pulse. In the drawings, the same or corresponding parts are designated by the same reference numerals. Figure 2
Claims (1)
スごとに順次シフトさせるデータシフト回路と、このデ
ータシフト回路からのデータが設定されるデータレジス
タと、このデータレジスタへ上記データを取り込むため
のトリガ信号を発生子るコンパレータと、アドレスを蓄
積したアドレスレジスタとで構成されたデータ設定装置
において、上記データレジスタにデータが設定されると
設定され、たデータを上記データシフト回路へ帰還させ
、このデータをただちに外部へ送出させるよう−に構成
したことを特徴とするデータ設定装置。A data shift circuit that sequentially shifts serial data that is input serially in time for each clock pulse, a data register to which data from this data shift circuit is set, and a trigger for loading the data into this data register. In a data setting device consisting of a comparator that generates a signal and an address register that stores addresses, when data is set in the data register, the set data is returned to the data shift circuit, and this data is A data setting device characterized in that the data setting device is configured to immediately send the data to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP110084U JPS60113572U (en) | 1984-01-09 | 1984-01-09 | Data setting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP110084U JPS60113572U (en) | 1984-01-09 | 1984-01-09 | Data setting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60113572U true JPS60113572U (en) | 1985-08-01 |
Family
ID=30473534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP110084U Pending JPS60113572U (en) | 1984-01-09 | 1984-01-09 | Data setting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113572U (en) |
-
1984
- 1984-01-09 JP JP110084U patent/JPS60113572U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60113572U (en) | Data setting device | |
| JPS6020695U (en) | Input signal detection circuit | |
| JPS60158250U (en) | data output device | |
| JPS59153596U (en) | Storage device | |
| JPS6142623U (en) | reset circuit | |
| JPS58101232U (en) | microcomputer | |
| JPS6090911U (en) | Digital waveform generator | |
| JPS5823433U (en) | noise suppression circuit | |
| JPS59118007U (en) | Output circuit | |
| JPS59147197U (en) | Reverberation effect device | |
| JPS5860398U (en) | Memory protect signal generator | |
| JPS5843654U (en) | Reference signal generation circuit | |
| JPS5986742U (en) | Programmable timing generation circuit | |
| JPS5832495U (en) | audio time clock | |
| JPS5847945U (en) | Request signal processing circuit | |
| JPS5891173U (en) | Peak level detection circuit | |
| JPS58107633U (en) | Output circuit | |
| JPS6140760U (en) | Digital signal correction device | |
| JPS5991042U (en) | Digital waveform discrimination circuit | |
| JPS6087050U (en) | data transfer control device | |
| JPS58109792U (en) | audio signal delay device | |
| JPS5823432U (en) | noise suppression circuit | |
| JPS5950175U (en) | remote control unit | |
| JPS5816933U (en) | Two-phase pulse generator | |
| JPS60114992U (en) | Electronic clock correction device |