JPS5860398U - Memory protect signal generator - Google Patents

Memory protect signal generator

Info

Publication number
JPS5860398U
JPS5860398U JP15284681U JP15284681U JPS5860398U JP S5860398 U JPS5860398 U JP S5860398U JP 15284681 U JP15284681 U JP 15284681U JP 15284681 U JP15284681 U JP 15284681U JP S5860398 U JPS5860398 U JP S5860398U
Authority
JP
Japan
Prior art keywords
circuit
protect signal
signal generator
memory protect
specific digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15284681U
Other languages
Japanese (ja)
Inventor
章 大庭
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP15284681U priority Critical patent/JPS5860398U/en
Publication of JPS5860398U publication Critical patent/JPS5860398U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のブロック図、第2図はメモ
リ空間の説明図である。 1・・・コンパレータ、2.3・・・ラッチ回路。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a memory space. 1... Comparator, 2.3... Latch circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アドレス信号の特定桁を一方の入力とする第1のアンド
回路と、このアドレス信号の特定桁の特定ビットを指定
する情報を記憶し、前記第1のアンド回路の他の入力へ
出力する第1のラッチ回路と、この特定桁のアドレスの
レベルを指定する情報を記憶する第2のラッチ回路と、
前記第1およ・び第2のラッチ回路の論理積出力を発す
る第2のアンド回路と、前記第1のアンド回路と第2の
アンド回路の出力を比較し一致をとりプロテクト信号を
発するコンパレータとを備えることを特徴とするメモリ
プロテクト信号発生装置。
a first AND circuit that receives a specific digit of the address signal as one input, and a first AND circuit that stores information specifying a specific bit of the specific digit of the address signal and outputs it to the other input of the first AND circuit. a second latch circuit that stores information specifying the level of the address of this specific digit;
a second AND circuit that generates an AND output of the first and second latch circuits, and a comparator that compares the outputs of the first AND circuit and the second AND circuit, finds a match, and generates a protect signal. A memory protect signal generating device comprising:
JP15284681U 1981-10-16 1981-10-16 Memory protect signal generator Pending JPS5860398U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15284681U JPS5860398U (en) 1981-10-16 1981-10-16 Memory protect signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15284681U JPS5860398U (en) 1981-10-16 1981-10-16 Memory protect signal generator

Publications (1)

Publication Number Publication Date
JPS5860398U true JPS5860398U (en) 1983-04-23

Family

ID=29945484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15284681U Pending JPS5860398U (en) 1981-10-16 1981-10-16 Memory protect signal generator

Country Status (1)

Country Link
JP (1) JPS5860398U (en)

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