JPS5897796U - conversion circuit - Google Patents

conversion circuit

Info

Publication number
JPS5897796U
JPS5897796U JP19128081U JP19128081U JPS5897796U JP S5897796 U JPS5897796 U JP S5897796U JP 19128081 U JP19128081 U JP 19128081U JP 19128081 U JP19128081 U JP 19128081U JP S5897796 U JPS5897796 U JP S5897796U
Authority
JP
Japan
Prior art keywords
data
ram
outputs
bit
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19128081U
Other languages
Japanese (ja)
Other versions
JPS6034159Y2 (en
Inventor
賢治 大西
Original Assignee
株式会社明電舎
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社明電舎 filed Critical 株式会社明電舎
Priority to JP19128081U priority Critical patent/JPS6034159Y2/en
Publication of JPS5897796U publication Critical patent/JPS5897796U/en
Application granted granted Critical
Publication of JPS6034159Y2 publication Critical patent/JPS6034159Y2/en
Expired legal-status Critical Current

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  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は、本考案の一実施例を示した構成図である。 １はＲＡＭ、２はＲＯＭ、３はレシーバ、４はデータセ
レクタ、５．６はデコーダ、７はドライバ、Ｆ１〜ＦＢ
はフリップフロップ。 １ １′２ （（The figure is a configuration diagram showing an embodiment of the present invention. 1 is RAM, 2 is ROM, 3 is receiver, 4 is data selector, 5.6 is decoder, 7 is driver, F1 to FB
is a flip-flop. 1 1'2 ((

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] Ｎビットのワードデータを記憶するＲＡＭから１ビツト
のデータを取り出し、１ビツトのデータを該ＲＡＭに記
憶させるものにおいて、前記ＲＡＭに信号を出力するＲ
ＯＭと、前記ＲＡＭからワードデータを入力して、デー
タセレクタ、ドライバーにデータを出力する複数のフリ
ップフロップに１ビツトつつ出力するレシーバと、ＲＯ
Ｍからの信号により前記ＲＡＭにデータを出力するドラ
イバと、印加するアドレスに基づいて１ビツトデータを
出力するデータセレクトと、１ビツトデータを入力し、
印加するアドレスに基づいて該当するフリップフロップ
に１ビツトデータを出力するデコーダとを備えたことを
特徴とする変換回路。In a device that extracts 1-bit data from a RAM that stores N-bit word data and stores 1-bit data in the RAM, an R that outputs a signal to the RAM is used.
OM, a receiver that inputs word data from the RAM and outputs one bit at a time to a plurality of flip-flops that output data to a data selector and driver, and an RO.
a driver that outputs data to the RAM in response to a signal from M; a data select that outputs 1-bit data based on an applied address; and a driver that inputs 1-bit data;
A conversion circuit comprising: a decoder that outputs 1-bit data to a corresponding flip-flop based on an applied address.
JP19128081U 1981-12-22 1981-12-22 conversion circuit Expired JPS6034159Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19128081U JPS6034159Y2 (en) 1981-12-22 1981-12-22 conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19128081U JPS6034159Y2 (en) 1981-12-22 1981-12-22 conversion circuit

Publications (2)

Publication Number Publication Date
JPS5897796U true JPS5897796U (en) 1983-07-02
JPS6034159Y2 JPS6034159Y2 (en) 1985-10-11

Family

ID=30104753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19128081U Expired JPS6034159Y2 (en) 1981-12-22 1981-12-22 conversion circuit

Country Status (1)

Country Link
JP (1) JPS6034159Y2 (en)

Also Published As

Publication number Publication date
JPS6034159Y2 (en) 1985-10-11

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