JPS59106229U - resampler - Google Patents
resamplerInfo
- Publication number
- JPS59106229U JPS59106229U JP63183U JP63183U JPS59106229U JP S59106229 U JPS59106229 U JP S59106229U JP 63183 U JP63183 U JP 63183U JP 63183 U JP63183 U JP 63183U JP S59106229 U JPS59106229 U JP S59106229U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- resampler
- analog switch
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例回路の構成図。第2図は本考案実施例回
路の構成図。
1・・・入力端子(PAM信号)、2・・・入力端子(
再標本化クロックパルス)、3・・・アナログスイッチ
回路、4・・・増幅器、5・・・出力端子、6・・・イ
ンバータ、7・・・可変抵抗器、8・・・コンデンサ、
9・・・可変抵抗器。 。FIG. 1 is a configuration diagram of a conventional circuit. FIG. 2 is a configuration diagram of a circuit according to an embodiment of the present invention. 1... Input terminal (PAM signal), 2... Input terminal (
resampling clock pulse), 3... analog switch circuit, 4... amplifier, 5... output terminal, 6... inverter, 7... variable resistor, 8... capacitor,
9...Variable resistor. .
Claims (1)
通路に挿入され、このパルス振幅変調信号に同期する信
号でオン・オフされるアナログスイッチ回路を備えた再
標本化器において、上記アナログスイッチ回路の制御信
号を分岐して極性が反転された振幅の小さい信号を造る
回路と、 この回路の出力を上記アナログスイッチ回路の出力信号
に加算する回路と を含むことを特徴とする再標本化器。[Claims for Utility Model Registration] A resampler equipped with an analog switch circuit that is inserted into the path of the output pulse amplitude modulation signal of the digital fist analog converter and is turned on and off by a signal synchronized with this pulse amplitude modulation signal. characterized in that it includes a circuit that branches the control signal of the analog switch circuit to create a signal with a small amplitude and whose polarity is inverted, and a circuit that adds the output of this circuit to the output signal of the analog switch circuit. resampler.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63183U JPS59106229U (en) | 1983-01-06 | 1983-01-06 | resampler |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63183U JPS59106229U (en) | 1983-01-06 | 1983-01-06 | resampler |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59106229U true JPS59106229U (en) | 1984-07-17 |
Family
ID=30132387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63183U Pending JPS59106229U (en) | 1983-01-06 | 1983-01-06 | resampler |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59106229U (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54102846A (en) * | 1978-01-30 | 1979-08-13 | Ricoh Co Ltd | Signal holding circuit |
JPS56146327A (en) * | 1980-04-15 | 1981-11-13 | Casio Comput Co Ltd | Output error compensating circuit for digital-to-analog converter |
JPS57166069A (en) * | 1981-04-07 | 1982-10-13 | Nec Corp | Analog switch |
-
1983
- 1983-01-06 JP JP63183U patent/JPS59106229U/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54102846A (en) * | 1978-01-30 | 1979-08-13 | Ricoh Co Ltd | Signal holding circuit |
JPS56146327A (en) * | 1980-04-15 | 1981-11-13 | Casio Comput Co Ltd | Output error compensating circuit for digital-to-analog converter |
JPS57166069A (en) * | 1981-04-07 | 1982-10-13 | Nec Corp | Analog switch |
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