JPS596334U

JPS596334U - Peak hold circuit

Info

Publication number: JPS596334U
Application number: JP1982100408U
Authority: JP
Inventors: 守田　陽一; 孝伊藤
Original assignee: 三菱電機株式会社
Priority date: 1982-06-30
Filing date: 1982-06-30
Publication date: 1984-01-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のピークホールド回路を示す回路構成図、
第２図は第１図のピークホールド回路におけ名各部の電
圧波形図、第３図は本考案の一実施例であるピークホー
ルド回路を示す回路構成図、第４図は第３図のピークホ
ールド回路における各部の電圧波形図である。１・・・入力端子、２・・・出力端子、５・・・コンデ
ンサ、６・・・アナログスイッチ、７・・・ポルチー？
コンパレ　゛−タ。なお、図中、同一符号は同一、又は
相当部分を示す。第３図第４図Figure 1 is a circuit diagram showing a conventional peak hold circuit.
Fig. 2 is a voltage waveform diagram of each part of the peak hold circuit shown in Fig. 1, Fig. 3 is a circuit configuration diagram showing a peak hold circuit which is an embodiment of the present invention, and Fig. 4 is a peak hold circuit diagram of the peak hold circuit shown in Fig. 3. FIG. 4 is a voltage waveform diagram of each part in the hold circuit. 1... Input terminal, 2... Output terminal, 5... Capacitor, 6... Analog switch, 7... Porty?
Comparator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 3 Figure 4

Claims

[Scope of utility model registration request]

(1) A capacitor for holding the peak voltage of the input signal; a control means for detecting the peak time of the input signal and generating a sampling pulse only at the peak time; A peak hold circuit comprising voltage applying means configured to apply a voltage of an input signal to the capacitor and hold the voltage of the capacitor while the sampling pulse does not appear.

(2) The peak hold circuit according to claim 1, wherein the control means is a voltage comparison means that compares the input signal with the voltage of a capacitor and generates the sampling pulse.

(3) The peak hold circuit according to claim 1 or 2, wherein an analog switch is used as the voltage applying means.

(4) As the voltage comparison means, a voltage comparator is used.
- the peak hold circuit according to claim 2 or 3 of the utility model registration claim, characterized in that the peak hold circuit uses a lattice filter;