JPS593631U - pulse shaping circuit - Google Patents

pulse shaping circuit

Info

Publication number
JPS593631U
JPS593631U JP9909482U JP9909482U JPS593631U JP S593631 U JPS593631 U JP S593631U JP 9909482 U JP9909482 U JP 9909482U JP 9909482 U JP9909482 U JP 9909482U JP S593631 U JPS593631 U JP S593631U
Authority
JP
Japan
Prior art keywords
pulse
peak value
circuit
comparator
shaping circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9909482U
Other languages
Japanese (ja)
Inventor
持田 勝見
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP9909482U priority Critical patent/JPS593631U/en
Publication of JPS593631U publication Critical patent/JPS593631U/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案パルス整形回路の一実施例を示す接続図
、第2図は本考案の動作を説明するためのタイムチャー
トである。 1・・・信号入力端子、2・・・信号出力端子、3・・
・ピーク値ホールド回路、4・・・フィルタ、5・・・
減算回L  6・吻・コンパレータ、■b・・・バイア
ス値、Vp・・・ピーク値。
FIG. 1 is a connection diagram showing one embodiment of the pulse shaping circuit of the present invention, and FIG. 2 is a time chart for explaining the operation of the present invention. 1...Signal input terminal, 2...Signal output terminal, 3...
・Peak value hold circuit, 4...filter, 5...
Subtraction times L 6. Proboscis/Comparator, ■b...Bias value, Vp...Peak value.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一方の入力端子にパルス入力が加えられ、他方の入力端
子に基準値が加えられて、出力端子にパルス力を波形整
形したパルス出力を発生するコンパレータと、前記パル
ス入力のピーク値をホール・ ドするピーク値ホールド
回路と、このピーク値から一定のバイアス値を減算する
回路と、この減算回路の出力を前記コンパレータに基準
値として与える手段とを備えたパルス整形回路。
A comparator is provided with a pulse input applied to one input terminal, a reference value is applied to the other input terminal, and generates a pulse output obtained by shaping the pulse force at the output terminal, and a comparator that holds the peak value of the pulse input. A pulse shaping circuit comprising: a peak value hold circuit for holding the peak value; a circuit for subtracting a constant bias value from the peak value; and means for applying the output of the subtraction circuit to the comparator as a reference value.
JP9909482U 1982-06-30 1982-06-30 pulse shaping circuit Pending JPS593631U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9909482U JPS593631U (en) 1982-06-30 1982-06-30 pulse shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9909482U JPS593631U (en) 1982-06-30 1982-06-30 pulse shaping circuit

Publications (1)

Publication Number Publication Date
JPS593631U true JPS593631U (en) 1984-01-11

Family

ID=30234985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9909482U Pending JPS593631U (en) 1982-06-30 1982-06-30 pulse shaping circuit

Country Status (1)

Country Link
JP (1) JPS593631U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828576U (en) * 1971-08-09 1973-04-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4828576U (en) * 1971-08-09 1973-04-07

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