JPS5848113U - Staircase waveform signal step reduction circuit - Google Patents
Staircase waveform signal step reduction circuitInfo
- Publication number
- JPS5848113U JPS5848113U JP14181581U JP14181581U JPS5848113U JP S5848113 U JPS5848113 U JP S5848113U JP 14181581 U JP14181581 U JP 14181581U JP 14181581 U JP14181581 U JP 14181581U JP S5848113 U JPS5848113 U JP S5848113U
- Authority
- JP
- Japan
- Prior art keywords
- waveform signal
- staircase waveform
- staircase
- reduction circuit
- step reduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例のブロック図。第２図ａ ”
−ｆは本考案の一実施例の作用の説明に供する波形図。
第３図は本考案の一実施例をステレオ復調回線として用
いたときの出力階段波形信号に含まれるキャリヤ側帯波
の量を示す特性図。
２．７および１１・・・・・・バッファ増幅器、３・・
・・・・２相パルス発振器、４および訃・曲スイッチ回
路、。 ６・・・・・・サンプルホールド回路からなる
階段波発生回路、１０・・・・・・サンプルホールド回
路からなる遅延回路、１２・・・・・・加算器。FIG. 1 is a block diagram of an embodiment of the present invention. Figure 2 a”
-f is a waveform diagram for explaining the operation of an embodiment of the present invention. FIG. 3 is a characteristic diagram showing the amount of carrier sideband included in the output staircase waveform signal when one embodiment of the present invention is used as a stereo demodulation line. 2.7 and 11...buffer amplifier, 3...
...2-phase pulse oscillator, 4, and a switch circuit. 6...Staircase wave generation circuit consisting of a sample and hold circuit, 10...Delay circuit consisting of a sample and hold circuit, 12...Adder.
Claims (1)
ルホールドして階段波形信号に変換する階段波発生回路
と、該階段波発生回路の出力階段波形信号を前記サンプ
リングパルスのｌ／２周期だけ遅延させる遅延回路と、
前記階段波信号発生回路の出力階段波形信号と前記遅延
回路の出力階段波形信号とを加算して出力する加算器と
を備えて−なることを特徴とする階段波形信号段差低減
回路。a staircase wave generation circuit that samples and holds an input signal using a sampling pulse of a constant period and converts it into a staircase waveform signal; and a delay circuit that delays the output staircase waveform signal of the staircase waveform signal by 1/2 period of the sampling pulse. ,
A step waveform signal step reduction circuit comprising: an adder that adds the output step waveform signal of the step wave signal generation circuit and the output step waveform signal of the delay circuit and outputs the result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14181581U JPS5848113U (en) | 1981-09-24 | 1981-09-24 | Staircase waveform signal step reduction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14181581U JPS5848113U (en) | 1981-09-24 | 1981-09-24 | Staircase waveform signal step reduction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5848113U true JPS5848113U (en) | 1983-03-31 |
| JPS6223158Y2 JPS6223158Y2 (en) | 1987-06-12 |
Family
ID=29934881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14181581U Granted JPS5848113U (en) | 1981-09-24 | 1981-09-24 | Staircase waveform signal step reduction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848113U (en) |
-
1981
- 1981-09-24 JP JP14181581U patent/JPS5848113U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6223158Y2 (en) | 1987-06-12 |
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