JPS5830999U - sample and hold circuit - Google Patents
sample and hold circuitInfo
- Publication number
- JPS5830999U JPS5830999U JP12404681U JP12404681U JPS5830999U JP S5830999 U JPS5830999 U JP S5830999U JP 12404681 U JP12404681 U JP 12404681U JP 12404681 U JP12404681 U JP 12404681U JP S5830999 U JPS5830999 U JP S5830999U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- circuit
- voltage
- sawtooth
- analog switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のサンプルアンドホールド回路の丙路図、
第２図ａないし第２図ｅは第１図のサンプルアンドホー
ルド回路の動作を説明するための′ タイムチャート、
第３図はこの考案のサンプルアンドホールド回路の一実
施例の回路図、第４図ａないし第４図ｄは第３図のサン
プルアンドホールド回路の動作を説明するためのタイム
チャート、第５図はこの考案のサンプルアンドホールド
回路の他の実施例を示す回路図である。
１・・・・・・リセット信号、２・・・・・・サンプル
信号、３・・・・・・リセット回路、４・・曲アナログ
スイッチ、５・・・・・・鋸歯状波発生回路、６・・・
・・・出力バッファ回路、７・・・・・・コンデンサ。Figure 1 is a cross-sectional diagram of a conventional sample-and-hold circuit.
Figures 2a to 2e are time charts for explaining the operation of the sample-and-hold circuit in Figure 1;
FIG. 3 is a circuit diagram of an embodiment of the sample-and-hold circuit of this invention, FIGS. 4a to 4d are time charts for explaining the operation of the sample-and-hold circuit of FIG. 3, and FIG. FIG. 2 is a circuit diagram showing another embodiment of the sample-and-hold circuit of this invention. 1... Reset signal, 2... Sample signal, 3... Reset circuit, 4... Song analog switch, 5... Sawtooth wave generation circuit, 6...
... Output buffer circuit, 7... Capacitor.
Claims (1)
と、このリセット回路のオフ時に出力電圧が上昇しかつ
リセット回路のオン時に出力電圧が漸減して鋸歯状波を
発生する鋸歯状波発生回路と、サンプル信号の到来時に
オンとなりかつサンプル信号のない期間オフとなるアナ
ログスイッチと、このアナログスイッチのオンの期間、
上記鋸歯状波発生回路で発生した鋸歯状電圧を充電する
とともに上記アナログスイッチのオフの期間この鋸歯状
波電圧を保持するホー・ルドコンデンサと、上記アナロ
グスイッチのオフの期間、上記ホールドコンデンサで保
持された鋸歯状波電圧を出力するＣＭＯ３ＩＣによる差
動アンプによる出力バッファ回路とよりなるサンプルア
ンドホールド回路。A reset circuit that turns on and off depending on the presence or absence of a reset signal, a sawtooth wave generation circuit that increases the output voltage when the reset circuit is off, and gradually decreases the output voltage when the reset circuit is on to generate a sawtooth wave, and a sample. an analog switch that is turned on when a signal arrives and is turned off during a period when there is no sample signal, and an on period of this analog switch;
A hold capacitor that charges the sawtooth voltage generated by the sawtooth wave generation circuit and holds this sawtooth voltage while the analog switch is off; and a hold capacitor that holds the sawtooth voltage while the analog switch is off. This sample-and-hold circuit consists of an output buffer circuit using a differential amplifier using a CMO3 IC that outputs a sawtooth wave voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12404681U JPS5830999U (en) | 1981-08-24 | 1981-08-24 | sample and hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12404681U JPS5830999U (en) | 1981-08-24 | 1981-08-24 | sample and hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5830999U true JPS5830999U (en) | 1983-02-28 |
Family
ID=29917934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12404681U Pending JPS5830999U (en) | 1981-08-24 | 1981-08-24 | sample and hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5830999U (en) |
-
1981
- 1981-08-24 JP JP12404681U patent/JPS5830999U/en active Pending
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