JPS5882044U - voltage timer circuit - Google Patents

voltage timer circuit

Info

Publication number
JPS5882044U
JPS5882044U JP17533281U JP17533281U JPS5882044U JP S5882044 U JPS5882044 U JP S5882044U JP 17533281 U JP17533281 U JP 17533281U JP 17533281 U JP17533281 U JP 17533281U JP S5882044 U JPS5882044 U JP S5882044U
Authority
JP
Japan
Prior art keywords
voltage
timer circuit
output
output voltage
voltage timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17533281U
Other languages
Japanese (ja)
Inventor
石井 重隆
和博 山田
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP17533281U priority Critical patent/JPS5882044U/en
Publication of JPS5882044U publication Critical patent/JPS5882044U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例、第2図は本考案の動作を説
明するタイミングチャートである。 1、 6. 10・・・・・・ナンド回路、2.11・
・・・・・インバータ、3,4,5,7,8,9. 1
2. 13゜14・・・・・・ic、15・・・・・・
ノア回路、16・・・・−ic演算増巾器、17・・・
・・−D−Aコンバータ、18〜2゜・・・・・・抵抗
、21・・・・・・コンデンサ。
FIG. 1 is an embodiment of the present invention, and FIG. 2 is a timing chart illustrating the operation of the present invention. 1, 6. 10... NAND circuit, 2.11.
...Inverter, 3, 4, 5, 7, 8, 9. 1
2. 13゜14...ic, 15...
NOR circuit, 16...-IC operational amplifier, 17...
...-D-A converter, 18~2°...Resistor, 21...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のディジタルicと、D−Aコンバータと、その出
力電圧を反転増巾させるic演算増巾器とから構成され
る電圧タイマー回路において、出力には上昇時および下
降時において共に時間に対する電圧変化率が一定なアナ
ログ電圧かえられ、さらに、出力電圧が飽和しない時点
で、入力信号が止まっても出力電圧はある一定の値を保
持するこぶができるように構成されたことを特徴とする
電圧タイマー回路。
In a voltage timer circuit composed of multiple digital ICs, a D-A converter, and an IC operational amplifier that inverts and amplifies the output voltage, the output has a voltage change rate with respect to time both when rising and falling. is changed to a constant analog voltage, and furthermore, the voltage timer circuit is configured such that at a point in time when the output voltage is not saturated, the output voltage maintains a constant value even if the input signal stops. .
JP17533281U 1981-11-27 1981-11-27 voltage timer circuit Pending JPS5882044U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17533281U JPS5882044U (en) 1981-11-27 1981-11-27 voltage timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17533281U JPS5882044U (en) 1981-11-27 1981-11-27 voltage timer circuit

Publications (1)

Publication Number Publication Date
JPS5882044U true JPS5882044U (en) 1983-06-03

Family

ID=29967652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17533281U Pending JPS5882044U (en) 1981-11-27 1981-11-27 voltage timer circuit

Country Status (1)

Country Link
JP (1) JPS5882044U (en)

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