JPS58149822U - flip-flop circuit - Google Patents

flip-flop circuit

Info

Publication number
JPS58149822U
JPS58149822U JP4499682U JP4499682U JPS58149822U JP S58149822 U JPS58149822 U JP S58149822U JP 4499682 U JP4499682 U JP 4499682U JP 4499682 U JP4499682 U JP 4499682U JP S58149822 U JPS58149822 U JP S58149822U
Authority
JP
Japan
Prior art keywords
comparator
flip
transistor
flop circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4499682U
Other languages
Japanese (ja)
Inventor
静雄 高橋
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP4499682U priority Critical patent/JPS58149822U/en
Publication of JPS58149822U publication Critical patent/JPS58149822U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフリップ・フロップ回路の一例を示す回
路図、第2図は本考案によるフリップ・フロップ回路の
一実施例を示す回路図、第3図a〜dは第2図に示す回
路の各部動作波形図である。 10.12・・・・・・コンパレータ、11,13゜1
5、 16. 18. 19・・・・・・抵抗、14.
17・・・・・・トランジスタ。
FIG. 1 is a circuit diagram showing an example of a conventional flip-flop circuit, FIG. 2 is a circuit diagram showing an embodiment of the flip-flop circuit according to the present invention, and FIGS. 3 a to d are the circuits shown in FIG. 2. FIG. 10.12...Comparator, 11,13゜1
5, 16. 18. 19...Resistance, 14.
17...Transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アナログセット入力およびアナログリセット入力をそれ
ぞれ基準値と比較する第1.第2のコンパレータと、こ
の第1のコンパレータ出力によって制御されて第2のら
ンパレータに対する基準値をその出力状態を安定化する
方向に切り替え制御す−る第1のトランジスタと、前記
第29コンパレータ出力によって制御されて第1のコン
パレータに対する基準値をその出力状態を安定する方向
に切り替え制御する第2のトランジスタとを備えたフリ
ップ会フロップ回路。
The first step is to compare the analog set input and analog reset input with respective reference values. a second comparator; a first transistor that is controlled by the first comparator output to switch a reference value for the second comparator in a direction that stabilizes its output state; and the twenty-ninth comparator output. a second transistor that is controlled by a second transistor to switch and control a reference value for the first comparator in a direction that stabilizes its output state.
JP4499682U 1982-03-31 1982-03-31 flip-flop circuit Pending JPS58149822U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4499682U JPS58149822U (en) 1982-03-31 1982-03-31 flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4499682U JPS58149822U (en) 1982-03-31 1982-03-31 flip-flop circuit

Publications (1)

Publication Number Publication Date
JPS58149822U true JPS58149822U (en) 1983-10-07

Family

ID=30056038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4499682U Pending JPS58149822U (en) 1982-03-31 1982-03-31 flip-flop circuit

Country Status (1)

Country Link
JP (1) JPS58149822U (en)

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