JPS5881655U - comparison circuit - Google Patents

comparison circuit

Info

Publication number
JPS5881655U
JPS5881655U JP17348481U JP17348481U JPS5881655U JP S5881655 U JPS5881655 U JP S5881655U JP 17348481 U JP17348481 U JP 17348481U JP 17348481 U JP17348481 U JP 17348481U JP S5881655 U JPS5881655 U JP S5881655U
Authority
JP
Japan
Prior art keywords
counters
counting
comparison circuit
digital signals
bit digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17348481U
Other languages
Japanese (ja)
Inventor
樋野 均
浜田 芳男
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP17348481U priority Critical patent/JPS5881655U/en
Publication of JPS5881655U publication Critical patent/JPS5881655U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の回路を示すブロック図、第2図はこの考
案の一実施例を示すブロック図である。 3・・・・・・カウンターf、3 a、 3 b、  
3 c、 3 a””それぞれカウンタ、4・・・・・
・オアゲート。なお、各図中同一符号は同−又は相当部
分を示す。 \
FIG. 1 is a block diagram showing a conventional circuit, and FIG. 2 is a block diagram showing an embodiment of this invention. 3... Counter f, 3 a, 3 b,
3 c, 3 a"" each counter, 4...
・Orgate. Note that the same reference numerals in each figure indicate the same or corresponding parts. \

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] nビットのディジタル信号m個のうちの最大又は最小の
ものを検出する比較回路において、並列入力端子を有す
るnビットのカウンタm個に上記nビットのディジタル
信号m個をそれぞれプリセットする手段と、このプリセ
ットしたm個のカウ□ンタに並列に同一クロックパルス
を送り上記m個のカウンタを同時にアップカウント又は
ダウンカウントする手段と、上記m個のカウンタのいず
れかのカウンタからオーバフローパルスが出力したとき
上記m個のカウンタのアップカウント又はダウンカウン
トを停止する手段とを備えたことを特徴とする比較回路
In a comparator circuit for detecting the maximum or minimum of m n-bit digital signals, means for presetting m n-bit counters each having parallel input terminals with the m n-bit digital signals; means for sending the same clock pulse to m preset counters in parallel and simultaneously up-counting or down-counting the m counters; and when an overflow pulse is output from any of the m counters. A comparison circuit comprising means for stopping up-counting or down-counting of m counters.
JP17348481U 1981-11-20 1981-11-20 comparison circuit Pending JPS5881655U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17348481U JPS5881655U (en) 1981-11-20 1981-11-20 comparison circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17348481U JPS5881655U (en) 1981-11-20 1981-11-20 comparison circuit

Publications (1)

Publication Number Publication Date
JPS5881655U true JPS5881655U (en) 1983-06-02

Family

ID=29965347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17348481U Pending JPS5881655U (en) 1981-11-20 1981-11-20 comparison circuit

Country Status (1)

Country Link
JP (1) JPS5881655U (en)

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