JPS6142417U - Count value display device - Google Patents
Count value display deviceInfo
- Publication number
- JPS6142417U JPS6142417U JP12721684U JP12721684U JPS6142417U JP S6142417 U JPS6142417 U JP S6142417U JP 12721684 U JP12721684 U JP 12721684U JP 12721684 U JP12721684 U JP 12721684U JP S6142417 U JPS6142417 U JP S6142417U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- count value
- signal
- output signal
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Indicating Measured Values (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の構成を示すブロック図、第
２図は従来例のブロック図である。
１・・・Ａ／Ｄ変換器、２・・・ラッチ回路、３・・・
表示ドライバ、４・・・表示部、５・・・比較回路、６
・・・クロツク発生回路、７・・・アンド回路、８・・
・乗除算器。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 1... A/D converter, 2... latch circuit, 3...
Display driver, 4...Display section, 5...Comparison circuit, 6
...Clock generation circuit, 7...AND circuit, 8...
- Multiplier/divider.
Claims (1)
からのデイジタル信号を保持するラッチ回路と、該ラッ
チ回路の出力信号を乗除算する乗除算器と、該乗除算器
の出力信号が入力され、表示部に計数値を表示させる表
示ドライバと、前記アナログ・デイジタル変換器からの
デイジタル信号とラッチ回路の出力信号とを比較し所定
値より大きいか等しいときに信号を出力する比較回路と
、該比較回路の出力信号とクロツク発生回路か′らのク
ロツク信号とのアンド条件が満たされたとき前記ラッチ
回路を制御するアンド回路とからなる計数値表示装置。An analog-to-digital converter for measurement input values, a latch circuit that holds the digital signal from the converter, a multiplier/divider that multiplies and divides the output signal of the latch circuit, and an output signal of the multiplier/divider is input. , a display driver that displays a count value on a display section, a comparison circuit that compares the digital signal from the analog-to-digital converter and the output signal of the latch circuit and outputs a signal when it is greater than or equal to a predetermined value; A count value display device comprising an AND circuit that controls the latch circuit when an AND condition between the output signal of the comparison circuit and the clock signal from the clock generation circuit is satisfied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12721684U JPS6142417U (en) | 1984-08-22 | 1984-08-22 | Count value display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12721684U JPS6142417U (en) | 1984-08-22 | 1984-08-22 | Count value display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142417U true JPS6142417U (en) | 1986-03-19 |
Family
ID=30685863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12721684U Pending JPS6142417U (en) | 1984-08-22 | 1984-08-22 | Count value display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142417U (en) |
-
1984
- 1984-08-22 JP JP12721684U patent/JPS6142417U/en active Pending
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