JPS5837212U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5837212U
JPS5837212U JP12980881U JP12980881U JPS5837212U JP S5837212 U JPS5837212 U JP S5837212U JP 12980881 U JP12980881 U JP 12980881U JP 12980881 U JP12980881 U JP 12980881U JP S5837212 U JPS5837212 U JP S5837212U
Authority
JP
Japan
Prior art keywords
transistor
muting
muting circuit
biasing
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12980881U
Other languages
Japanese (ja)
Inventor
坂本　章治
Original Assignee
三洋電機株式会社
鳥取三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社, 鳥取三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP12980881U priority Critical patent/JPS5837212U/en
Publication of JPS5837212U publication Critical patent/JPS5837212U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案のミューティング回路を示す図、第２図
は第１図要部の波形図である。 ＳＷ・・・Ｗスイッチ、Ｔｒｌ・・・ミューティング制
御信号発生用トランジスタ、Ｔｒ２・・・ミューティン
グ用ｌ・ランジスタ、Ｌ・・・信号ライン。FIG. 1 is a diagram showing the muting circuit of the present invention, and FIG. 2 is a waveform diagram of the main part of FIG. 1. SW...W switch, Trl...transistor for generating a muting control signal, Tr2...L transistor for muting, L...signal line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ゛べ一戎電極にコンデンサーと抵抗よりなる充電回路が
接続されてバイアスされ、又エミッタ電極にコンデンサ
ーと放電防止用ダイオードよりなる充電回路が接続され
てバイアスされ、且つコレクタ電極からミューティング
制御信号を出力するトランジスタと、該トランジスタよ
りのミューティング制御信号により導通され、信号ライ
ンを接地するトランジスタで構成したことを特徴とする
ミューティング回路。A charging circuit consisting of a capacitor and a resistor is connected to one electrode for biasing, and a charging circuit consisting of a capacitor and a discharge prevention diode is connected to the emitter electrode for biasing, and a muting control signal is transmitted from the collector electrode. A muting circuit comprising: a transistor that outputs an output; and a transistor that is made conductive by a muting control signal from the transistor and grounds a signal line.
JP12980881U 1981-08-31 1981-08-31 Muting circuit Pending JPS5837212U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12980881U JPS5837212U (en) 1981-08-31 1981-08-31 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12980881U JPS5837212U (en) 1981-08-31 1981-08-31 Muting circuit

Publications (1)

Publication Number Publication Date
JPS5837212U true JPS5837212U (en) 1983-03-10

Family

ID=29923470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12980881U Pending JPS5837212U (en) 1981-08-31 1981-08-31 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5837212U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59103408A (en) * 1982-12-03 1984-06-14 Matsushita Electric Ind Co Ltd Muting device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50841B1 (en) * 1970-03-10 1975-01-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50841B1 (en) * 1970-03-10 1975-01-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59103408A (en) * 1982-12-03 1984-06-14 Matsushita Electric Ind Co Ltd Muting device

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