JPS59106214U - Logarithmic amplifier drift compensation circuit - Google Patents
Logarithmic amplifier drift compensation circuitInfo
- Publication number
- JPS59106214U JPS59106214U JP19710782U JP19710782U JPS59106214U JP S59106214 U JPS59106214 U JP S59106214U JP 19710782 U JP19710782 U JP 19710782U JP 19710782 U JP19710782 U JP 19710782U JP S59106214 U JPS59106214 U JP S59106214U
- Authority
- JP
- Japan
- Prior art keywords
- logarithmic amplifier
- drift compensation
- compensation circuit
- input
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の対数増幅器の概略構成図、第2図は本考
案の一実施例の概略構成図、第3図は第2図のタイミン
グスケジュールである。
3:対数増幅器、4ニドリフト補償回路、5:演算増幅
器、6:積分回路。FIG. 1 is a schematic diagram of a conventional logarithmic amplifier, FIG. 2 is a schematic diagram of an embodiment of the present invention, and FIG. 3 is a timing schedule of FIG. 3: logarithmic amplifier, 4: drift compensation circuit, 5: operational amplifier, 6: integrating circuit.
Claims (1)
ッチと、前記スイッチにより前記入力信号が入力されこ
の入力信号に関係した出力をする対数増幅器と、前記対
数増幅器の出力側に接続される演算増幅器と、この演算
増幅器の出力側に接続され前記スイッチの切換により前
記基準電圧が前記対数増幅器に入力された際の前記演算
増幅器の出力を前記演算増幅器の入力側に負帰還して、
ドリフト補償する積分回路とを備えたことを特徴とする
対数増幅器のドリフト補償回路。a switch that repeatedly and periodically switches an input signal and a reference voltage; a logarithmic amplifier to which the input signal is input by the switch and outputs an output related to the input signal; and an operational amplifier connected to the output side of the logarithmic amplifier; Negatively feeding back the output of the operational amplifier when the reference voltage is input to the logarithmic amplifier by switching the switch connected to the output side of the operational amplifier, to the input side of the operational amplifier;
1. A logarithmic amplifier drift compensation circuit, comprising: an integrator circuit for drift compensation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19710782U JPS59106214U (en) | 1982-12-31 | 1982-12-31 | Logarithmic amplifier drift compensation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19710782U JPS59106214U (en) | 1982-12-31 | 1982-12-31 | Logarithmic amplifier drift compensation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59106214U true JPS59106214U (en) | 1984-07-17 |
Family
ID=30422444
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19710782U Pending JPS59106214U (en) | 1982-12-31 | 1982-12-31 | Logarithmic amplifier drift compensation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59106214U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183347A (en) * | 1991-12-28 | 1993-07-23 | Nec Corp | Signal processing circuit for semiconductor sensor |
-
1982
- 1982-12-31 JP JP19710782U patent/JPS59106214U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05183347A (en) * | 1991-12-28 | 1993-07-23 | Nec Corp | Signal processing circuit for semiconductor sensor |
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