JPS60170857U - Asynchronous signal receiver - Google Patents
Asynchronous signal receiverInfo
- Publication number
- JPS60170857U JPS60170857U JP5606984U JP5606984U JPS60170857U JP S60170857 U JPS60170857 U JP S60170857U JP 5606984 U JP5606984 U JP 5606984U JP 5606984 U JP5606984 U JP 5606984U JP S60170857 U JPS60170857 U JP S60170857U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gate
- circuit
- output
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ変換について説明するためのブロ
ック図、第２図はこの考案の一実施例を示すブロック図
、第３図は第１図の主要部分のタイムチャート、第４図
は第２図の主要部分のタイムチャートである。
図において１は判定回路、２は変換回路、７はフリップ
フロップ、８はレジスタである。尚、図中同一符号は同
一または相当部分を示すものとする。Fig. 1 is a block diagram for explaining conventional data conversion, Fig. 2 is a block diagram showing an embodiment of this invention, Fig. 3 is a time chart of the main parts of Fig. 1, and Fig. 4 is a block diagram for explaining the conventional data conversion. 2 is a time chart of the main parts of FIG. In the figure, 1 is a determination circuit, 2 is a conversion circuit, 7 is a flip-flop, and 8 is a register. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
る判定回路と、入力される非同期直列データと上記同期
信号とで上記直列データを並列データに変換し出力する
変換回路と、上記判定回路の出力信号と準備信号を入力
し、その論理積を取るゲートと、このゲートの出力信号
と上記準備信号を入力しその状態を保持し出力するフリ
ップフロップと、このフリップフロップの出力信号によ
り上記変換回路より出力される並列データを入力し保持
するレジスタとからなり、上記判定回路の出力信号と上
記準備信号とで制御される上記ゲートと上記フリップフ
ロップとで上記変換回路の出力データを保持する事を特
徴とした非同期信号受信装置。A determination circuit that determines the presence or absence of an input synchronization signal and outputs the result; a conversion circuit that converts the serial data into parallel data using the input asynchronous serial data and the synchronization signal and outputs the same; and the determination circuit. A gate that inputs the output signal and the preparation signal of the gate and takes the logical product; a flip-flop that inputs the output signal of this gate and the preparation signal, holds the state, and outputs it; and the output signal of this flip-flop performs the above conversion. It consists of a register that inputs and holds parallel data output from the circuit, and the output data of the conversion circuit is held by the gate and the flip-flop, which are controlled by the output signal of the judgment circuit and the preparation signal. An asynchronous signal receiving device featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5606984U JPS60170857U (en) | 1984-04-17 | 1984-04-17 | Asynchronous signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5606984U JPS60170857U (en) | 1984-04-17 | 1984-04-17 | Asynchronous signal receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60170857U true JPS60170857U (en) | 1985-11-12 |
Family
ID=30579327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5606984U Pending JPS60170857U (en) | 1984-04-17 | 1984-04-17 | Asynchronous signal receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60170857U (en) |
-
1984
- 1984-04-17 JP JP5606984U patent/JPS60170857U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60170857U (en) | Asynchronous signal receiver | |
| JPS58123393U (en) | electronic time switch | |
| JPS58124895U (en) | Alarm signal holding circuit | |
| JPS5914449U (en) | Synchronous signal input circuit | |
| JPS60145738U (en) | Synchronous circuit for asynchronous signals and pulse signals | |
| JPS6020695U (en) | Input signal detection circuit | |
| JPS60135868U (en) | Video signal processing circuit | |
| JPS617151U (en) | synchronization circuit | |
| JPS6140043U (en) | Differential A/D converter | |
| JPS58127765U (en) | Image signal sampling pulse generation circuit | |
| JPS594006U (en) | Duplex pulse output processing device | |
| JPS5882039U (en) | phase comparison circuit | |
| JPS60116549U (en) | Main/slave computer synchronization device | |
| JPS5846193U (en) | logic input circuit | |
| JPS58191769U (en) | Synchronous signal switching circuit | |
| JPS58538U (en) | Data speed conversion circuit | |
| JPS5996610U (en) | Bus abnormality detection circuit | |
| JPS6047356U (en) | Signal polarity conversion circuit | |
| JPS6066176U (en) | Clamp level control circuit | |
| JPS6017032U (en) | Pulse extraction circuit | |
| JPS63169733U (en) | ||
| JPS59187778U (en) | signal input device | |
| JPS59153588U (en) | Muting circuit of monitor receiver | |
| JPS5927632U (en) | A/D converter | |
| JPS59192741U (en) | CMI code clock extraction circuit |