JPS58174706U - sampling control device - Google Patents

sampling control device

Info

Publication number
JPS58174706U
JPS58174706U JP4133783U JP4133783U JPS58174706U JP S58174706 U JPS58174706 U JP S58174706U JP 4133783 U JP4133783 U JP 4133783U JP 4133783 U JP4133783 U JP 4133783U JP S58174706 U JPS58174706 U JP S58174706U
Authority
JP
Japan
Prior art keywords
output
circuit
amplifier circuit
control device
sampling control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4133783U
Other languages
Japanese (ja)
Inventor
千尋 岡土
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP4133783U priority Critical patent/JPS58174706U/en
Publication of JPS58174706U publication Critical patent/JPS58174706U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はサンプリング制御による速度基準波形を示す図
、第2図〜第4図はそれぞれ異るサンプリング制御時の
速度基準波形図、第5図は本考案   ゛の一実施例を
示すブロック図、第6図は同実施例の具体的な回路図、
第7図は第5図および第6図の動作を説明するためのタ
イムチャート、第8図〜第10図は本考案の他の実施例
を示すものでブロック図、波形図およびブロック図であ
る。 IN・・・・・・サンプリング出力、OUT・・・・・
・最終出力、COM・・・・・・比較回路、AMP・・
・・・・増幅回路、INT・・・・・・積分回路、SH
T・・・・・・ワンショット回路、M・・・・・・メモ
リ回路、LM・・・・・・リミット回路。
FIG. 1 is a diagram showing a speed reference waveform under sampling control, FIGS. 2 to 4 are speed reference waveform diagrams under different sampling controls, and FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 6 is a specific circuit diagram of the same embodiment,
FIG. 7 is a time chart for explaining the operations in FIGS. 5 and 6, and FIGS. 8 to 10 are block diagrams, waveform diagrams, and block diagrams showing other embodiments of the present invention. . IN... Sampling output, OUT...
・Final output, COM... Comparison circuit, AMP...
...Amplifier circuit, INT...Integrator circuit, SH
T: one-shot circuit, M: memory circuit, LM: limit circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一定時間間隔で次々とステップ状に変化する目標値信号
をランプ状に変化する出力信号に変換するものにおいて
、前記目標値信号と前記出力信号を比較する比較回路と
、この比較回路の出力を前記一定の時間隔でサンプリン
グしてその間記憶するメモリ回路と、前記比較回路の出
力を増幅する増幅回路と、この増幅回路の出力及び前記
メモリ回路の出力を異なる極性で加算する加算手段と、
この加算手段の出力を一定値以内に制限して前記増幅回
路に与えるリミッタ−と、前記増幅回路の出力を積分す
る積分回路とからなることを特徴とするサンプリング制
御装置。
A device for converting a target value signal that changes step by step at regular time intervals into an output signal that changes like a ramp, includes a comparison circuit that compares the target value signal and the output signal; a memory circuit that samples at regular time intervals and stores it during that time; an amplifier circuit that amplifies the output of the comparison circuit; and an adding means that adds the output of the amplifier circuit and the output of the memory circuit with different polarities;
A sampling control device comprising: a limiter that limits the output of the adding means to within a certain value and applies it to the amplifier circuit; and an integrating circuit that integrates the output of the amplifier circuit.
JP4133783U 1983-03-24 1983-03-24 sampling control device Pending JPS58174706U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4133783U JPS58174706U (en) 1983-03-24 1983-03-24 sampling control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4133783U JPS58174706U (en) 1983-03-24 1983-03-24 sampling control device

Publications (1)

Publication Number Publication Date
JPS58174706U true JPS58174706U (en) 1983-11-22

Family

ID=30052520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4133783U Pending JPS58174706U (en) 1983-03-24 1983-03-24 sampling control device

Country Status (1)

Country Link
JP (1) JPS58174706U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50116881A (en) * 1974-01-23 1975-09-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50116881A (en) * 1974-01-23 1975-09-12

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