JPS59147352U - Reception level detection device - Google Patents

Reception level detection device

Info

Publication number
JPS59147352U
JPS59147352U JP1983041501U JP4150183U JPS59147352U JP S59147352 U JPS59147352 U JP S59147352U JP 1983041501 U JP1983041501 U JP 1983041501U JP 4150183 U JP4150183 U JP 4150183U JP S59147352 U JPS59147352 U JP S59147352U
Authority
JP
Japan
Prior art keywords
detection device
reception level
level detection
detection circuit
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983041501U
Other languages
Japanese (ja)
Inventor
茂 田中
室園 章貴
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP1983041501U priority Critical patent/JPS59147352U/en
Publication of JPS59147352U publication Critical patent/JPS59147352U/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の受信レベル検出回路の一構成図、第2図
はこの考案の受信レベル検出装置の一実施例図、第3図
は第1図および第2図の波形説明図である。 1・・・受信信号レベル検出回路、2・・・サンプル・
ホールド回路、3a、  3b、  3c・・・電圧比
較器。なお、図中、同一符号は同一、又は相当部分を示
す。
FIG. 1 is a block diagram of a conventional reception level detection circuit, FIG. 2 is a diagram of an embodiment of the reception level detection device of this invention, and FIG. 3 is a waveform explanatory diagram of FIGS. 1 and 2. 1... Received signal level detection circuit, 2... Sample
Hold circuit, 3a, 3b, 3c...voltage comparator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 一定の周期内で複数のレベルに変換する受信信号を検出
する検出回路と、この検出回路の出力を各周期毎に1回
の割合で且つ異なるレベルをサンプリングするサンプル
ホールド回路とを備えた受信レベル検出装置。
A reception level that includes a detection circuit that detects a received signal that is converted into a plurality of levels within a certain period, and a sample and hold circuit that samples the output of this detection circuit at a different level once every period. Detection device.
JP1983041501U 1983-03-22 1983-03-22 Reception level detection device Pending JPS59147352U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983041501U JPS59147352U (en) 1983-03-22 1983-03-22 Reception level detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983041501U JPS59147352U (en) 1983-03-22 1983-03-22 Reception level detection device

Publications (1)

Publication Number Publication Date
JPS59147352U true JPS59147352U (en) 1984-10-02

Family

ID=30172077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983041501U Pending JPS59147352U (en) 1983-03-22 1983-03-22 Reception level detection device

Country Status (1)

Country Link
JP (1) JPS59147352U (en)

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