JPS5961667U - DC component regeneration circuit - Google Patents

DC component regeneration circuit

Info

Publication number
JPS5961667U
JPS5961667U JP15507682U JP15507682U JPS5961667U JP S5961667 U JPS5961667 U JP S5961667U JP 15507682 U JP15507682 U JP 15507682U JP 15507682 U JP15507682 U JP 15507682U JP S5961667 U JPS5961667 U JP S5961667U
Authority
JP
Japan
Prior art keywords
signal
regeneration circuit
component regeneration
level
inputting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15507682U
Other languages
Japanese (ja)
Inventor
幸美 佐伯
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP15507682U priority Critical patent/JPS5961667U/en
Publication of JPS5961667U publication Critical patent/JPS5961667U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、第２図ａ、　
　ｂ、　　ｃは第１図の各部の電圧波形を示す波形図で
ある。 １・・・直流レベル挿入回路、２・・・直流再生回路、
３・・・入力端子。Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2a,
b and c are waveform diagrams showing voltage waveforms at various parts in FIG. 1; 1... DC level insertion circuit, 2... DC regeneration circuit,
3...Input terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 任意の信号を入力する信号入力端子と、該信号と同期し
たタイミング信号を入力するタイミング信号入力端子を
有し、該タイミング信号と同期した期間、該入力信号に
任意の直流レベルを挿入し、該挿入された直流レベルを
基準にして、信号の直流レベルを再生することを特徴と
する直流分再生回路。It has a signal input terminal for inputting an arbitrary signal and a timing signal input terminal for inputting a timing signal synchronized with the signal, and an arbitrary DC level is inserted into the input signal during a period synchronized with the timing signal. A DC component regeneration circuit characterized by regenerating the DC level of a signal based on the inserted DC level.
JP15507682U 1982-10-15 1982-10-15 DC component regeneration circuit Pending JPS5961667U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15507682U JPS5961667U (en) 1982-10-15 1982-10-15 DC component regeneration circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15507682U JPS5961667U (en) 1982-10-15 1982-10-15 DC component regeneration circuit

Publications (1)

Publication Number Publication Date
JPS5961667U true JPS5961667U (en) 1984-04-23

Family

ID=30342597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15507682U Pending JPS5961667U (en) 1982-10-15 1982-10-15 DC component regeneration circuit

Country Status (1)

Country Link
JP (1) JPS5961667U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107270U (en) * 1984-12-17 1986-07-08

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107270U (en) * 1984-12-17 1986-07-08

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