JPS59119668U - Frame pulse generation circuit - Google Patents
Frame pulse generation circuitInfo
- Publication number
- JPS59119668U JPS59119668U JP1309583U JP1309583U JPS59119668U JP S59119668 U JPS59119668 U JP S59119668U JP 1309583 U JP1309583 U JP 1309583U JP 1309583 U JP1309583 U JP 1309583U JP S59119668 U JPS59119668 U JP S59119668U
- Authority
- JP
- Japan
- Prior art keywords
- output
- frame pulse
- generation circuit
- pulse generation
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のフレーム、パルス発生回路のブロック図
、第２図は第１図のブロックの動作波形図、第３図は本
考案の実施例のブロック図、第４図は第３図のブロック
の動作波形図である。Fig. 1 is a block diagram of a conventional frame and pulse generation circuit, Fig. 2 is an operation waveform diagram of the block in Fig. 1, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram of the block in Fig. 3. FIG. 3 is an operation waveform diagram of the block.
Claims (1)
手段と、前記複合同期信号から等価パルスを除去する等
価パルス除去手段と、前記比較手段の比較出力のレベル
遷移タイミングによって前記等価パルス除去手段の出力
をラッチするラッチ手段とを誉み、このラッチ出力を用
いてフレームパルスを発生するようにしたフレームパル
ス発生回路であって、前記等価パルス除去手段の出力の
レベル遷移タイミングによって前記ラッチ出力を更にラ
ッチする別のラッチ手段を設け、この別のラッチ手段の
出力をフレームパルスとしてなるフレームパルス発生回
路。a comparison means for comparing the integrated output of the composite synchronization signal with a reference level; an equivalent pulse removal means for removing the equivalent pulse from the composite synchronization signal; A frame pulse generation circuit is provided with a latch means for latching the output, and the latch output is used to generate a frame pulse, and the latch output is further generated by the level transition timing of the output of the equivalent pulse removal means. A frame pulse generation circuit that is provided with another latch means for latching, and uses the output of this other latch means as a frame pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1309583U JPS59119668U (en) | 1983-02-01 | 1983-02-01 | Frame pulse generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1309583U JPS59119668U (en) | 1983-02-01 | 1983-02-01 | Frame pulse generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59119668U true JPS59119668U (en) | 1984-08-13 |
| JPH026705Y2 JPH026705Y2 (en) | 1990-02-19 |
Family
ID=30144486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1309583U Granted JPS59119668U (en) | 1983-02-01 | 1983-02-01 | Frame pulse generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119668U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5579575A (en) * | 1978-12-04 | 1980-06-16 | Philips Nv | Vertical synchronizing signal separating circuit for television |
| JPS57190480A (en) * | 1981-05-19 | 1982-11-24 | Victor Co Of Japan Ltd | Synchronizing signal processing circuit |
-
1983
- 1983-02-01 JP JP1309583U patent/JPS59119668U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5579575A (en) * | 1978-12-04 | 1980-06-16 | Philips Nv | Vertical synchronizing signal separating circuit for television |
| JPS57190480A (en) * | 1981-05-19 | 1982-11-24 | Victor Co Of Japan Ltd | Synchronizing signal processing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH026705Y2 (en) | 1990-02-19 |
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