JPS6123771U - clamp circuit - Google Patents
clamp circuitInfo
- Publication number
- JPS6123771U JPS6123771U JP10847084U JP10847084U JPS6123771U JP S6123771 U JPS6123771 U JP S6123771U JP 10847084 U JP10847084 U JP 10847084U JP 10847084 U JP10847084 U JP 10847084U JP S6123771 U JPS6123771 U JP S6123771U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- clamp circuit
- difference
- holding
- difference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Picture Signal Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のクランプ回路を示す回路図、第２図は
、第１図の回路の動作を示す波形図、第３図は、第１図
の回路の周波数特性を示すグラフ、第４図は、本発明の
一実施例を示す回路図、第５図は、第４図の回路の動作
を示す波形図、第６図は、第４図の回路の周波数特性を
示すグラフである。
主要部分の符号の説明、３・・・・・・保持回路、５・
・・・・・差信号発生回路、８・・・・・・加算器。FIG. 1 is a circuit diagram showing a conventional clamp circuit, FIG. 2 is a waveform diagram showing the operation of the circuit in FIG. 1, FIG. 3 is a graph showing the frequency characteristics of the circuit in FIG. 1, and FIG. 5 is a waveform diagram showing the operation of the circuit shown in FIG. 4, and FIG. 6 is a graph showing the frequency characteristics of the circuit shown in FIG. 4. Explanation of symbols of main parts, 3...Holding circuit, 5.
...Difference signal generation circuit, 8...Adder.
Claims (1)
する保持手段と、前記保持手段の出力と所定基準レベル
との差に応じた差信号を発生する差信号発生手段と、前
記差信号と前記入力信号とを合成する合成手段とからな
ることを特徴とするクランプ回路。holding means for holding and outputting an instantaneous level of an input signal at a predetermined timing; difference signal generating means for generating a difference signal according to the difference between the output of the holding means and a predetermined reference level; and the difference signal and the input. 1. A clamp circuit comprising a synthesis means for synthesizing a signal and a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10847084U JPS6123771U (en) | 1984-07-18 | 1984-07-18 | clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10847084U JPS6123771U (en) | 1984-07-18 | 1984-07-18 | clamp circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6123771U true JPS6123771U (en) | 1986-02-12 |
Family
ID=30667657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10847084U Pending JPS6123771U (en) | 1984-07-18 | 1984-07-18 | clamp circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123771U (en) |
-
1984
- 1984-07-18 JP JP10847084U patent/JPS6123771U/en active Pending
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