JPS5814173U - Peak hold circuit - Google Patents
Peak hold circuitInfo
- Publication number
- JPS5814173U JPS5814173U JP10666581U JP10666581U JPS5814173U JP S5814173 U JPS5814173 U JP S5814173U JP 10666581 U JP10666581 U JP 10666581U JP 10666581 U JP10666581 U JP 10666581U JP S5814173 U JPS5814173 U JP S5814173U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- hold circuit
- peak hold
- converter
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のヒーークホールド回路、第２図ｃ１本考
案によるピークホールド回路例及び第３図はその各細波
形を示す。FIG. 1 shows a conventional peak hold circuit, FIG. 2 shows an example of a peak hold circuit according to the present invention, and FIG. 3 shows each thin waveform thereof.
Claims (1)
して充電されるコンデンサの保持電圧とを比較する比較
器と、前記アナログ入力信号をディジタル化するＡ／Ｄ
コンバータとを有し、前記比較器は一方の出力レベルで
前記スイッチをオンにすると共に前記ディジタル化を行
わせ、他方の出力レベルでは前記スイッチをオフにする
と共に前記ディジタル化を停止させることを特徴とする
ピークホールド回路。 （２＞Ａ／Ｄコンバータのサンプリング用パルスを入力
とし、かつ比較器の出力で開閉制御されるゲートの出力
が、スイッチ及びＡ／Ｄコンバータに供給されることを
特徴とする実用新案登録請求の範囲第１項記載のピーク
ホールド回路。(1) A comparator that compares an analog input signal with the holding voltage of a capacitor charged through a switch by this signal, and an A/D that digitizes the analog input signal.
converter, wherein the comparator turns on the switch and causes the digitization to occur at one output level, and turns off the switch and stops the digitization at the other output level. Peak hold circuit. (2> Utility model registration request characterized in that the output of a gate whose input is a sampling pulse of an A/D converter and whose opening/closing is controlled by the output of a comparator is supplied to a switch and an A/D converter) Peak hold circuit according to range 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10666581U JPS5814173U (en) | 1981-07-20 | 1981-07-20 | Peak hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10666581U JPS5814173U (en) | 1981-07-20 | 1981-07-20 | Peak hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5814173U true JPS5814173U (en) | 1983-01-28 |
Family
ID=29901131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10666581U Pending JPS5814173U (en) | 1981-07-20 | 1981-07-20 | Peak hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814173U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6450527U (en) * | 1987-09-25 | 1989-03-29 |
-
1981
- 1981-07-20 JP JP10666581U patent/JPS5814173U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6450527U (en) * | 1987-09-25 | 1989-03-29 | ||
| JPH0446419Y2 (en) * | 1987-09-25 | 1992-10-30 |
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