JPS61149491U - - Google Patents
Info
- Publication number
- JPS61149491U JPS61149491U JP3226585U JP3226585U JPS61149491U JP S61149491 U JPS61149491 U JP S61149491U JP 3226585 U JP3226585 U JP 3226585U JP 3226585 U JP3226585 U JP 3226585U JP S61149491 U JPS61149491 U JP S61149491U
- Authority
- JP
- Japan
- Prior art keywords
- sample
- output
- hold
- buffer amplifier
- input buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000003638 chemical reducing agent Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はデジタルコンバーゼンス回路のブロツ
ク図、第２図はＤ／Ａコンバータ入力の各位ビツ
トの波形図、第３図はＤ／Ａコンバータの出力波
形図、第４図はサンプルホールド回路の回路構成
図、第５図は上記サンプルホールド回路中のスイ
ツチの開閉動作を説明するための開閉状態図、第
６図は上記サンプルホールド回路のセツトリング
タイムｔｓを指示するためのパルス応答波形図で
ある。
４……サンプルホールド回路、５……低域波
器、１０……アナログ信号、１１……サンプルホ
ールド出力、１７……入力バツフアアンプ、１９
……実効抵抗、２０……ホールド用コンデンサ、
２１……出力バツフアアンブ。
Figure 1 is a block diagram of the digital convergence circuit, Figure 2 is a waveform diagram of each bit input to the D/A converter, Figure 3 is a diagram of the output waveform of the D/A converter, and Figure 4 is the circuit configuration of the sample and hold circuit. 5 is an open/close state diagram for explaining the opening/closing operation of the switch in the sample hold circuit, and FIG. 6 is a pulse response waveform diagram for instructing the settling time ts of the sample hold circuit. 4... Sample hold circuit, 5... Low frequency device, 10... Analog signal, 11... Sample hold output, 17... Input buffer amplifier, 19
...Effective resistance, 20...Hold capacitor,
21... Output buffer amplifier.
Claims (1)
この入力バツフアアンプの出力により充電される
ホールドコンデンサと、このホールドコンデンサ
の端子電圧が供給される出力バツフアアンプとを
有し、前記出力バツフアアンプの出力するサンプ
ルホールド出力の供給を受けこれを補間する低減
波器が後段に接続されるサンプルホールド回路
において、前記ホールドコンデンサの容量値Ｃを （Ｃ＞ｔ２Ｒ・１ｎ（１００／Ｅ）） ｔ２：サンプル時間、 Ｒ：サンプルホールド回路の入力バツフアから
見た実効抵抗値、 Ｅ：サンプルホールド出力のセツトリングタイ
ムにおける目標収束値に対する誤差、 に設定したことを特徴とするサンプルホールド回
路。[Claims for Utility Model Registration] An input buffer amplifier that receives an analog signal, a hold capacitor that is charged by the output of the input buffer amplifier, and an output buffer amplifier that is supplied with the terminal voltage of the hold capacitor; In a sample and hold circuit in which a wave reducer is connected at a subsequent stage to receive and interpolate the sample and hold output to be output, the capacitance value C of the hold capacitor is defined as (C>t 2 R・1n(100/E)) t 2 : sample time; R: effective resistance value seen from the input buffer of the sample-hold circuit; and E: error with respect to a target convergence value in settling time of the sample-hold output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3226585U JPS61149491U (en) | 1985-03-08 | 1985-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3226585U JPS61149491U (en) | 1985-03-08 | 1985-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61149491U true JPS61149491U (en) | 1986-09-16 |
Family
ID=30533622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3226585U Pending JPS61149491U (en) | 1985-03-08 | 1985-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61149491U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142907A (en) * | 1986-11-28 | 1988-06-15 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Radio freouency modulated signal decoder |
| JP2000134096A (en) * | 1998-10-27 | 2000-05-12 | Nec Corp | Successive comparison type a/d converter |
-
1985
- 1985-03-08 JP JP3226585U patent/JPS61149491U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63142907A (en) * | 1986-11-28 | 1988-06-15 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | Radio freouency modulated signal decoder |
| JP2000134096A (en) * | 1998-10-27 | 2000-05-12 | Nec Corp | Successive comparison type a/d converter |
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