JPH01105212U - - Google Patents

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Publication number
JPH01105212U
JPH01105212U JP20143987U JP20143987U JPH01105212U JP H01105212 U JPH01105212 U JP H01105212U JP 20143987 U JP20143987 U JP 20143987U JP 20143987 U JP20143987 U JP 20143987U JP H01105212 U JPH01105212 U JP H01105212U
Authority
JP
Japan
Prior art keywords
circuit
voltage
pulse width
signal
converts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20143987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20143987U priority Critical patent/JPH01105212U/ja
Publication of JPH01105212U publication Critical patent/JPH01105212U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の1実施例の電圧制御回路のブ
ロツク図、第2図は第1図のパルス幅変換回路の
具体的構成図、第3図は第2図の回路の各部の波
形図、第4図は第1図の電圧設定回路の回路図、
第5図は第1図のスイツチング回路の具体的回路
図、第6図は第1図のスイツチング回路の具体的
回路図である。 1……入力端子、2……パルス幅変調回路、3
……スイツチング回路、4……電圧設定回路、5
……ローパスフイルタ、7……出力端子。
Fig. 1 is a block diagram of a voltage control circuit according to an embodiment of the present invention, Fig. 2 is a specific configuration diagram of the pulse width conversion circuit of Fig. 1, and Fig. 3 is a waveform diagram of each part of the circuit of Fig. 2. , FIG. 4 is a circuit diagram of the voltage setting circuit of FIG. 1,
5 is a specific circuit diagram of the switching circuit shown in FIG. 1, and FIG. 6 is a specific circuit diagram of the switching circuit shown in FIG. 1. 1...Input terminal, 2...Pulse width modulation circuit, 3
... Switching circuit, 4 ... Voltage setting circuit, 5
...Low pass filter, 7...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧制御すべき電圧信号を入力する入力端子と
、この入力端子に入力される電圧信号をその電位
に相応したパルス幅の反復パルス信号に変換する
パルス幅変調回路と、このパルス幅変調回路から
出力される反復パルス信号の電圧振幅を所定のレ
ベルに変換するスイツチング回路と、このスイツ
チング回路における電圧振幅の変換レベルを設定
する電圧設定回路と、上記スイツチング回路によ
り電圧振幅の設定された反復パルス信号をパルス
幅に相応した電圧信号に変換するフイルタ回路と
からなる電圧制御回路。
An input terminal for inputting a voltage signal to be controlled, a pulse width modulation circuit for converting the voltage signal input to this input terminal into a repetitive pulse signal with a pulse width corresponding to the potential, and an output from this pulse width modulation circuit. a switching circuit that converts the voltage amplitude of the repetitive pulse signal to a predetermined level; a voltage setting circuit that sets the conversion level of the voltage amplitude in the switching circuit; A voltage control circuit consisting of a filter circuit that converts into a voltage signal corresponding to the pulse width.
JP20143987U 1987-12-30 1987-12-30 Pending JPH01105212U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20143987U JPH01105212U (en) 1987-12-30 1987-12-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20143987U JPH01105212U (en) 1987-12-30 1987-12-30

Publications (1)

Publication Number Publication Date
JPH01105212U true JPH01105212U (en) 1989-07-14

Family

ID=31491798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20143987U Pending JPH01105212U (en) 1987-12-30 1987-12-30

Country Status (1)

Country Link
JP (1) JPH01105212U (en)

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