JPH0288336U - - Google Patents
Info
- Publication number
- JPH0288336U JPH0288336U JP16657388U JP16657388U JPH0288336U JP H0288336 U JPH0288336 U JP H0288336U JP 16657388 U JP16657388 U JP 16657388U JP 16657388 U JP16657388 U JP 16657388U JP H0288336 U JPH0288336 U JP H0288336U
- Authority
- JP
- Japan
- Prior art keywords
- output
- pulse width
- width modulation
- modulation circuit
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案に係る変換器の一実施例の接続
図、第２図は第１図変換器の動作を説明する為の
波形図、第３図は第１図変換器に用いられるリト
リガブル・マルチバイブレータの動作を説明する
為の波形図、第４図は従来のこの種の変換器の一
例の接続図である。
２０……ＰＷＭ回路、３３……カウンタ、５０
……トトリガブル・マルチバイブレータ。
Fig. 1 is a connection diagram of an embodiment of the converter according to the present invention, Fig. 2 is a waveform diagram for explaining the operation of the converter shown in Fig. 1, and Fig. 3 is a retriggerable waveform used in the converter shown in Fig. 1.・A waveform diagram for explaining the operation of the multivibrator. FIG. 4 is a connection diagram of an example of a conventional converter of this type. 20...PWM circuit, 33...Counter, 50
...Triggerable multivibrator.
Claims (1)
変調信号電圧を積分する積分器、この積分器の出
力が加えられるコンパレーター、このコンパレー
ターの出力で前記正、負の基準電源を切換える帰
還回路よりなるパルス幅変調回路、 このパルス幅変調回路の出力をデイジタル的に
計数するカウンタ、及び、 前記パルス幅変調回路の出力端子に接続されレ
ンジオーバーの検出手段として用いられるリトリ
ガブル・マルチバイブレータを具備したアナログ
・デイジタル変換器。[Claims for Utility Model Registration] An integrator that integrates the analog input to be converted, positive and negative reference power supplies and modulation signal voltages, a comparator to which the output of this integrator is added, and an output of the comparator that integrates the positive, A pulse width modulation circuit consisting of a feedback circuit that switches a negative reference power supply, a counter that digitally counts the output of this pulse width modulation circuit, and a counter that is connected to the output terminal of the pulse width modulation circuit and used as a range over detection means. Analog to digital converter equipped with a retriggerable multivibrator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16657388U JPH0288336U (en) | 1988-12-23 | 1988-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16657388U JPH0288336U (en) | 1988-12-23 | 1988-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0288336U true JPH0288336U (en) | 1990-07-12 |
Family
ID=31454077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16657388U Pending JPH0288336U (en) | 1988-12-23 | 1988-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0288336U (en) |
-
1988
- 1988-12-23 JP JP16657388U patent/JPH0288336U/ja active Pending
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