JPS6123738U - D/A converter - Google Patents
D/A converterInfo
- Publication number
- JPS6123738U JPS6123738U JP10663184U JP10663184U JPS6123738U JP S6123738 U JPS6123738 U JP S6123738U JP 10663184 U JP10663184 U JP 10663184U JP 10663184 U JP10663184 U JP 10663184U JP S6123738 U JPS6123738 U JP S6123738U
- Authority
- JP
- Japan
- Prior art keywords
- charging
- discharging circuit
- converter
- circuit
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案のＤ／Ａコンバータの構成を示す図、第
２図は同、信号出力電圧の周波数特性図、第３図は従来
のＤ／Ａコンバータの構成を示す図、第４図は同、信号
波形図である。
１はＤ／Ａ変換器、７は充放電回路、１３はデグリツチ
ャー回路、１５はローバスフィルタ、１８は固定抵抗、
１９はミラー積分回路である。Fig. 1 is a diagram showing the configuration of the D/A converter of the present invention, Fig. 2 is a frequency characteristic diagram of the signal output voltage, Fig. 3 is a diagram showing the configuration of a conventional D/A converter, and Fig. 4 is a signal waveform diagram. 1 is a D/A converter, 7 is a charging/discharging circuit, 13 is a deglitcher circuit, 15 is a low-pass filter, 18 is a fixed resistor,
19 is a Miller integration circuit.
Claims (1)
を出力するＤ／Ａ変換器１と、当該Ｄ／Ａ変換器１から
の一定電流を積分して上記入力データに対応したアナロ
グ電圧を出力する充放電回路７と、当該充放電回路７の
出力端子に固定抵抗１８を介して負電圧を供給して当該
充放電回路７の出力信号から直流成分を除去する手段と
、当該充放電回路７の出力信号を所定の制御信号に同期
してサンプル抽出するデグリツチャー回路１３と、当該
デグリツチャー回路１３の出力信号をアナログ信号に変
換するローバスフィルタ１５とを具備し、上記アナログ
信号から所定の周波数以下の超低周波成分および直流成
分を検出し、増幅した後、上記充放電回路７へ負帰還す
る増幅型負帰還ループを形成したＤ／Ａコンバータ。A D/A converter 1 obtains a time width proportional to the input data and outputs a constant current during that period, and the constant current from the D/A converter 1 is integrated to generate an analog voltage corresponding to the input data. A charging/discharging circuit 7 that outputs an output, a means for supplying a negative voltage to an output terminal of the charging/discharging circuit 7 via a fixed resistor 18 to remove a DC component from an output signal of the charging/discharging circuit 7, and a charging/discharging circuit 7, and a low-pass filter 15 that converts the output signal of the deglitcher circuit 13 into an analog signal. A D/A converter that forms an amplification type negative feedback loop that detects and amplifies the following extremely low frequency components and DC components, and then provides negative feedback to the charging/discharging circuit 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10663184U JPS6123738U (en) | 1984-07-13 | 1984-07-13 | D/A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10663184U JPS6123738U (en) | 1984-07-13 | 1984-07-13 | D/A converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6123738U true JPS6123738U (en) | 1986-02-12 |
Family
ID=30665911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10663184U Pending JPS6123738U (en) | 1984-07-13 | 1984-07-13 | D/A converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123738U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58147232A (en) * | 1982-02-26 | 1983-09-02 | Nec Home Electronics Ltd | Digital audio disk player |
-
1984
- 1984-07-13 JP JP10663184U patent/JPS6123738U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58147232A (en) * | 1982-02-26 | 1983-09-02 | Nec Home Electronics Ltd | Digital audio disk player |
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