JPS59119642U - double pulse oscillator - Google Patents
double pulse oscillatorInfo
- Publication number
- JPS59119642U JPS59119642U JP1265883U JP1265883U JPS59119642U JP S59119642 U JPS59119642 U JP S59119642U JP 1265883 U JP1265883 U JP 1265883U JP 1265883 U JP1265883 U JP 1265883U JP S59119642 U JPS59119642 U JP S59119642U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- terminal
- input terminal
- double pulse
- pulse oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案に係るダブルパルス発振器の一実施例を
示す回路図、第２図は動作説明のための波形図である。
Ａ１及びＡ２・・・演算増幅器（コンパレータ）、Ｒ□
〜Ｒ５・・・抵抗、Ｃ・・・コンデンサ。FIG. 1 is a circuit diagram showing an embodiment of the double pulse oscillator according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation. A1 and A2... operational amplifier (comparator), R□
~R5...Resistance, C...Capacitor.
Claims (1)
方の増幅器Ａ□のコンパレート点にヒステリシスを設け
、他方の増幅器Ａ２の動作点を前記ヒステリシスの中間
点に設定し、増幅器Ａ□の（＋）入力端子と増幅器Ａ２
の（−）入力端子に一定電圧Ｖ１を、また増幅器Ａ２の
（＋）入力端子に基準電圧ｖ２をそれぞれ加え、増幅器
Ａ１の反転出力Ｑ１を増幅器Ａ１の（＋）入力端子にフ
ィードバックする一方、反転出力Ｑ□を積分する回路を
設け、その積分出力を増幅器Ａ１の（−）入力端子に加
え、増幅器Ａ□のＱ□端子と増幅器Ａ２のＱ２端子また
は増幅器Ａ１のＱ１端子と増幅器Ａ２のＱ２端子から９
０”位相差のダブルパルスを取出すようにしたことを特
徴とするダブルパルス発振器。Hysteresis is provided at the comparison point of one amplifier A□ of two operational amplifiers A1゜A2 as comparators, and the operating point of the other amplifier A2 is set at the midpoint of the hysteresis, and the (+) Input terminal and amplifier A2
A constant voltage V1 is applied to the (-) input terminal of the amplifier A2, and a reference voltage v2 is applied to the (+) input terminal of the amplifier A2, and the inverted output Q1 of the amplifier A1 is fed back to the (+) input terminal of the amplifier A1. A circuit that integrates the output Q□ is provided, and the integrated output is applied to the (-) input terminal of the amplifier A1, and the Q□ terminal of the amplifier A□ and the Q2 terminal of the amplifier A2, or the Q1 terminal of the amplifier A1 and the Q2 terminal of the amplifier A2 are connected. From 9
A double pulse oscillator characterized in that it extracts a double pulse with a phase difference of 0''.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1265883U JPS59119642U (en) | 1983-01-31 | 1983-01-31 | double pulse oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1265883U JPS59119642U (en) | 1983-01-31 | 1983-01-31 | double pulse oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59119642U true JPS59119642U (en) | 1984-08-13 |
Family
ID=30144056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1265883U Pending JPS59119642U (en) | 1983-01-31 | 1983-01-31 | double pulse oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119642U (en) |
-
1983
- 1983-01-31 JP JP1265883U patent/JPS59119642U/en active Pending
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