JPS59144909U - frequency modulation circuit - Google Patents

frequency modulation circuit

Info

Publication number
JPS59144909U
JPS59144909U JP3981983U JP3981983U JPS59144909U JP S59144909 U JPS59144909 U JP S59144909U JP 3981983 U JP3981983 U JP 3981983U JP 3981983 U JP3981983 U JP 3981983U JP S59144909 U JPS59144909 U JP S59144909U
Authority
JP
Japan
Prior art keywords
modulation circuit
frequency modulation
variable capacitance
capacitance diode
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3981983U
Other languages
Japanese (ja)
Inventor
井上 秋男
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP3981983U priority Critical patent/JPS59144909U/en
Publication of JPS59144909U publication Critical patent/JPS59144909U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の周波数変調回路を示す図、第2図は可変
容量ダイオードに信号を印加したときの容量変化を示す
特性図、第3図は本考案に係る周波数変調回路の一実施
例を示す回路図、第4図イはトランジスタQ1のベース
電位とコレクタtiとの関係を示す特性図、第4図口は
トランジスタQ1に信号が印加されたときのコレクタ出
力電圧の変化を示す特性図、第4図ハは可変容量ダイオ
ードD□に第4図口の信号が印加されたときの可変容量
ダイオードD1の容量変化を示す特性図である。第5図
は本考案の他の実施例を示す回路図、第6図イはトラン
ジスタQ、/のベース電位とコレクタ電流との関係を示
す特性図、第6図口はトランジスタQ1′に信号が印加
されたときのコレクタ出力電圧の変化を示す特性図、第
6図ハは可変容量ダイオードD□に第6図口の信号が印
加されたときの可変容量ダイオードD□の容量変化を示
す特性図である。 Dl・・・・・・可変容量ダイオード、Q、、 Q□′
・・・・・・低周波増幅用トランジスタ。
Fig. 1 is a diagram showing a conventional frequency modulation circuit, Fig. 2 is a characteristic diagram showing capacitance changes when a signal is applied to a variable capacitance diode, and Fig. 3 is an example of a frequency modulation circuit according to the present invention. 4A is a characteristic diagram showing the relationship between the base potential of the transistor Q1 and the collector ti; FIG. FIG. 4C is a characteristic diagram showing the capacitance change of the variable capacitance diode D1 when the signal shown in FIG. 4 is applied to the variable capacitance diode D□. Fig. 5 is a circuit diagram showing another embodiment of the present invention, Fig. 6 A is a characteristic diagram showing the relationship between the base potential and collector current of transistor Q, and Fig. Figure 6 C is a characteristic diagram showing the change in the collector output voltage when the voltage is applied to the variable capacitance diode D□. It is. Dl...Variable capacitance diode, Q,, Q□'
・・・・・・Transistor for low frequency amplification.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 可変容量ダイオードを使用した周波数変調回路−に於い
て、前記可変容量ダイオードで発生する歪と逆極性の歪
を前記可変容量ダイオードの入力側に設けた低周波増幅
用トランジスタで発生させ、前記可変容量ダイオードで
発生する歪を打消すように構成したことを特徴とする周
波数変調回路。
In a frequency modulation circuit using a variable capacitance diode, a low frequency amplification transistor provided on the input side of the variable capacitance diode generates distortion of opposite polarity to the distortion generated by the variable capacitance diode, and A frequency modulation circuit characterized by being configured to cancel distortion generated by a diode.
JP3981983U 1983-03-18 1983-03-18 frequency modulation circuit Pending JPS59144909U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3981983U JPS59144909U (en) 1983-03-18 1983-03-18 frequency modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3981983U JPS59144909U (en) 1983-03-18 1983-03-18 frequency modulation circuit

Publications (1)

Publication Number Publication Date
JPS59144909U true JPS59144909U (en) 1984-09-27

Family

ID=30170454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3981983U Pending JPS59144909U (en) 1983-03-18 1983-03-18 frequency modulation circuit

Country Status (1)

Country Link
JP (1) JPS59144909U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52124850A (en) * 1976-04-13 1977-10-20 Mitsubishi Electric Corp Frequency modulation circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52124850A (en) * 1976-04-13 1977-10-20 Mitsubishi Electric Corp Frequency modulation circuit

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