JPS5933316U - amplifier circuit - Google Patents

amplifier circuit

Info

Publication number
JPS5933316U
JPS5933316U JP12957082U JP12957082U JPS5933316U JP S5933316 U JPS5933316 U JP S5933316U JP 12957082 U JP12957082 U JP 12957082U JP 12957082 U JP12957082 U JP 12957082U JP S5933316 U JPS5933316 U JP S5933316U
Authority
JP
Japan
Prior art keywords
amplifier circuit
feedback resistor
inverting input
output terminal
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12957082U
Other languages
Japanese (ja)
Other versions
JPS6223137Y2 (en
Inventor
有三 碓井
修一 井上
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP12957082U priority Critical patent/JPS5933316U/en
Publication of JPS5933316U publication Critical patent/JPS5933316U/en
Application granted granted Critical
Publication of JPS6223137Y2 publication Critical patent/JPS6223137Y2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａは従来のオフセット調整専用端子付演算増幅器
による非反転増幅回路のブロック図、第１図すは従来の
オフセット調整専用端子を備えない演算増幅器による非
反転増幅回路のブ冶ツク図および第２図は本考案の一実
施例におけるオフセット調整専用端子を備えない演算増
幅器による非反転増幅器によるブロック図である。 図において、１ｂはオフセット調整専用端子を備えない
演算増幅器、Ｃはコンデンサ、ＶＲは可　　−変抵抗器
およびＲｆは帰還抵抗器である。Figure 1a is a block diagram of a conventional non-inverting amplifier circuit using an operational amplifier with a terminal dedicated to offset adjustment; FIG. 2 is a block diagram of a non-inverting amplifier using an operational amplifier without a dedicated offset adjustment terminal in an embodiment of the present invention. In the figure, 1b is an operational amplifier without a terminal dedicated to offset adjustment, C is a capacitor, VR is a variable resistor, and Rf is a feedback resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 演算増幅器による非反転増幅回路において、該増幅回路
の出力端子により反転入力端子に接続する帰還抵抗の出
力端子側にコンデンサを直列接続し、該帰還抵抗を介し
反転入力端子にオフセット調整電圧を印加する手段を設
けたことを特徴とする増幅回路。In a non-inverting amplifier circuit using an operational amplifier, a capacitor is connected in series to the output terminal side of a feedback resistor connected to an inverting input terminal by an output terminal of the amplifier circuit, and an offset adjustment voltage is applied to the inverting input terminal via the feedback resistor. An amplifier circuit characterized by comprising means.
JP12957082U 1982-08-27 1982-08-27 amplifier circuit Granted JPS5933316U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12957082U JPS5933316U (en) 1982-08-27 1982-08-27 amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12957082U JPS5933316U (en) 1982-08-27 1982-08-27 amplifier circuit

Publications (2)

Publication Number Publication Date
JPS5933316U true JPS5933316U (en) 1984-03-01
JPS6223137Y2 JPS6223137Y2 (en) 1987-06-12

Family

ID=30293544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12957082U Granted JPS5933316U (en) 1982-08-27 1982-08-27 amplifier circuit

Country Status (1)

Country Link
JP (1) JPS5933316U (en)

Also Published As

Publication number Publication date
JPS6223137Y2 (en) 1987-06-12

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