JPS593611U

JPS593611U - Pulse width modulation amplifier circuit

Info

Publication number: JPS593611U
Application number: JP9793682U
Authority: JP
Inventors: 健司横山
Original assignee: ヤマハ株式会社
Priority date: 1982-06-29
Filing date: 1982-06-29
Publication date: 1984-01-11
Also published as: JPH0336099Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のパルス幅変調増幅回路の一例の構成を示
す回路図、第２図は同例の動作を説明するための波形図
、第３図は従来のパルス幅変調増幅回路の他の例の構成
を示す回路図、第４図は同例の動作を説明するための波
形図、第５図はこの考案の第１の実施例の構成を示す回
路図、第６図はこの考案の第２の実施例の構成を示す回
路図、第７図はこの考案の第３の実施例の構成を示す回
路図である。３・・・・・・パルス幅変調回路、１３・・・・・くラ
ー積分回路、１８・・・・・・ヒステリシスコンパレー
タ、１９・・・・・・抵抗、２０・・・・・・発振部、
２１・・・・・・トリガフリップフロップＵＫフリップ
フロップ）、２３・・・・・・可変周波数発振回路。Fig. 1 is a circuit diagram showing the configuration of an example of a conventional pulse width modulation amplification circuit, Fig. 2 is a waveform diagram for explaining the operation of the same example, and Fig. 3 is a circuit diagram showing the configuration of an example of a conventional pulse width modulation amplification circuit. FIG. 4 is a waveform diagram to explain the operation of the example; FIG. 5 is a circuit diagram showing the configuration of the first embodiment of the invention; FIG. 6 is a circuit diagram of the invention. FIG. 7 is a circuit diagram showing the structure of the second embodiment, and FIG. 7 is a circuit diagram showing the structure of the third embodiment of this invention. 3...Pulse width modulation circuit, 13...Kuller integration circuit, 18...Hysteresis comparator, 19...Resistor, 20...Oscillation Department,
21...Trigger flip-flop UK flip-flop), 23...Variable frequency oscillation circuit.

Claims

[Scope of utility model registration request]

In a pulse width modulation amplification circuit that pulse width modulates a carrier signal according to the amplitude of a signal to be amplified and amplifies the signal to be amplified as a pulse signal, a Miller integration circuit and a hysteresis comparator are sequentially connected in cascade, and the A variable frequency oscillation circuit is provided, which is composed of an oscillation section configured by feeding back the output of the hysteresis comparator to the Miller integration circuit, and a trigger flip-flop that inputs the output of the hysteresis comparator as a trigger signal, and A pulse width modulation amplification circuit characterized in that a signal proportional to is supplied as an input signal to the Miller integration circuit, and an output of the trigger flip-flop is used as the carrier signal.