JPS594025U - constant current circuit - Google Patents

constant current circuit

Info

Publication number
JPS594025U
JPS594025U JP9691182U JP9691182U JPS594025U JP S594025 U JPS594025 U JP S594025U JP 9691182 U JP9691182 U JP 9691182U JP 9691182 U JP9691182 U JP 9691182U JP S594025 U JPS594025 U JP S594025U
Authority
JP
Japan
Prior art keywords
input terminal
inverting input
circuit
integrator
constant current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9691182U
Other languages
Japanese (ja)
Inventor
山口 衛
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP9691182U priority Critical patent/JPS594025U/en
Publication of JPS594025U publication Critical patent/JPS594025U/en
Pending legal-status Critical Current

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  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Dc-Dc Converters (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の回路図、第2図は第1図の動作波形図、
第3図は本考案の実施例の回路図、第4図は第3図回路
の動作波形図である。 1G・・・積分器、U2・・・コンパレータ、Lo・・
・負荷、R2,C2・・・積分回路用抵抗およびキャパ
シタ。
Figure 1 is a conventional circuit diagram, Figure 2 is an operating waveform diagram of Figure 1,
FIG. 3 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is an operating waveform diagram of the circuit shown in FIG. 1G... Integrator, U2... Comparator, Lo...
- Load, R2, C2... Resistor and capacitor for the integration circuit.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)クロック電圧とフィードバック電圧を反転入力端
子に受け、非反転入力端子に基準電圧が加えられる増幅
器を有し面入力端子に印加される電圧の差を積分する積
分器、この積分器の出力が反転入力端子に加えられるコ
ンパレータ、このコンパレータが出力するパルス幅変調
信号によってスイッチングされるトランジスタ、このト
ランジスタに直列に接続された負荷、および、この負荷
に流れる電流を検出し前記フィードバック電圧を発生さ
せる電流検出抵抗を具備する回路において、前記積分器
と負荷の遅れに相当する遅れ時定数を有する積分回路を
設け、前記基準電圧をこの積分回路を介して前記コンパ
レータの非反転入力端子にフィードフォワードしてなる
定電流回路。
(1) An integrator that has an amplifier that receives a clock voltage and a feedback voltage at its inverting input terminal and applies a reference voltage to its non-inverting input terminal, and integrates the difference between the voltages applied to its plane input terminal; the output of this integrator is applied to the inverting input terminal, a transistor that is switched by the pulse width modulation signal outputted by this comparator, a load connected in series to this transistor, and a current flowing through this load is detected to generate the feedback voltage. In the circuit including a current detection resistor, an integrating circuit having a delay time constant corresponding to the delay of the integrator and the load is provided, and the reference voltage is fed forward to the non-inverting input terminal of the comparator through the integrating circuit. Constant current circuit.
(2)前記基準電圧の変化を微分したのち増幅し、この
増幅出力を前記積分回路を介して前記コンパレータの非
反転入力端子にフィードフォーワードしてなる実用新案
登録請求範囲第(1)項記載の定電流回路。
(2) Utility model registration claimed in claim (1), wherein the change in the reference voltage is differentiated and then amplified, and the amplified output is fed forward to the non-inverting input terminal of the comparator via the integrating circuit. constant current circuit.
JP9691182U 1982-06-28 1982-06-28 constant current circuit Pending JPS594025U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9691182U JPS594025U (en) 1982-06-28 1982-06-28 constant current circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9691182U JPS594025U (en) 1982-06-28 1982-06-28 constant current circuit

Publications (1)

Publication Number Publication Date
JPS594025U true JPS594025U (en) 1984-01-11

Family

ID=30230747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9691182U Pending JPS594025U (en) 1982-06-28 1982-06-28 constant current circuit

Country Status (1)

Country Link
JP (1) JPS594025U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225554A (en) * 1975-08-20 1977-02-25 Sharp Corp Pulse width modulation system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225554A (en) * 1975-08-20 1977-02-25 Sharp Corp Pulse width modulation system

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