JPS59157321U - Shock noise prevention circuit - Google Patents

Shock noise prevention circuit

Info

Publication number
JPS59157321U
JPS59157321U JP5206683U JP5206683U JPS59157321U JP S59157321 U JPS59157321 U JP S59157321U JP 5206683 U JP5206683 U JP 5206683U JP 5206683 U JP5206683 U JP 5206683U JP S59157321 U JPS59157321 U JP S59157321U
Authority
JP
Japan
Prior art keywords
inverting input
input terminal
output
signal path
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5206683U
Other languages
Japanese (ja)
Other versions
JPH0413848Y2 (en
Inventor
和久 石黒
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP5206683U priority Critical patent/JPS59157321U/en
Publication of JPS59157321U publication Critical patent/JPS59157321U/en
Application granted granted Critical
Publication of JPH0413848Y2 publication Critical patent/JPH0413848Y2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の反転入力型負帰還差動増幅器を示す回
路図、第2図は本考案の一実施例を示す回路図、及び第
3図イ乃至ホはその各部の電圧を示す特性図である。 主な図番の説明、12・・・差動増幅部、13・・・反
転入力端子、14・・・非反転入力端子、15・・・出
力端子、24・・・遅延回路、27.28・・・トラン
ジスタ。
Fig. 1 is a circuit diagram showing a conventional inverting input type negative feedback differential amplifier, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 A to E show characteristics showing voltages at various parts thereof. It is a diagram. Explanation of main figure numbers, 12...Differential amplifier section, 13...Inverting input terminal, 14...Non-inverting input terminal, 15...Output terminal, 24...Delay circuit, 27.28 ...Transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 反転入力端子と非反転入力端子と出力端子とを備え、前
記反転入力端子に入力コンデンサ及び入力抵抗を介して
入力信号を印加するとともに、帰還抵抗を介して前記出
力端子に得られる出力信号を負帰還し、前記非反転入力
端子にバイアス電圧を印加する様にした反転入力型負帰
還差動増幅器において、前記バイアス電圧を前記反転入
力端子に印加す−る為の第1信号路と、前記バイアス電
圧を遅延すること無く発生させる第2信号路と、前記バ
イアス電圧を遅延させる為の遅延回路を含む第3信号路
と、前記第2信号路の出力電圧と前記第3信号路の出力
電圧とを比較する比較回路と、該比較回路の出力信号に
応じて前記非反転入力端子を接地する為の接地回路とか
ら成るショック音防止回路。
It has an inverting input terminal, a non-inverting input terminal, and an output terminal, and an input signal is applied to the inverting input terminal through an input capacitor and an input resistor, and an output signal obtained at the output terminal is applied to the inverting input terminal through a feedback resistor. In an inverting input type negative feedback differential amplifier configured to feed back and apply a bias voltage to the non-inverting input terminal, a first signal path for applying the bias voltage to the inverting input terminal; a second signal path for generating voltage without delay; a third signal path including a delay circuit for delaying the bias voltage; an output voltage of the second signal path; and an output voltage of the third signal path. and a grounding circuit for grounding the non-inverting input terminal according to the output signal of the comparison circuit.
JP5206683U 1983-04-07 1983-04-07 Shock noise prevention circuit Granted JPS59157321U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5206683U JPS59157321U (en) 1983-04-07 1983-04-07 Shock noise prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5206683U JPS59157321U (en) 1983-04-07 1983-04-07 Shock noise prevention circuit

Publications (2)

Publication Number Publication Date
JPS59157321U true JPS59157321U (en) 1984-10-22
JPH0413848Y2 JPH0413848Y2 (en) 1992-03-30

Family

ID=30182436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5206683U Granted JPS59157321U (en) 1983-04-07 1983-04-07 Shock noise prevention circuit

Country Status (1)

Country Link
JP (1) JPS59157321U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140340U (en) * 1974-05-08 1975-11-19
JPS51131140U (en) * 1975-04-16 1976-10-22
JPS56142117U (en) * 1980-03-27 1981-10-27

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50140340U (en) * 1974-05-08 1975-11-19
JPS51131140U (en) * 1975-04-16 1976-10-22
JPS56142117U (en) * 1980-03-27 1981-10-27

Also Published As

Publication number Publication date
JPH0413848Y2 (en) 1992-03-30

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