JPS5848154U - Separation degree adjustment circuit - Google Patents
Separation degree adjustment circuitInfo
- Publication number
- JPS5848154U JPS5848154U JP14181681U JP14181681U JPS5848154U JP S5848154 U JPS5848154 U JP S5848154U JP 14181681 U JP14181681 U JP 14181681U JP 14181681 U JP14181681 U JP 14181681U JP S5848154 U JPS5848154 U JP S5848154U
- Authority
- JP
- Japan
- Prior art keywords
- inverting input
- input terminal
- adjustment circuit
- channel signal
- signal voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａ ”−’ ｅは従来の分離度調整回路のブロッ
ク図。第２図は本考案の一実施例の分離度調整回路のブ
ロック図。
２１および２２・・・・・・演算増幅器、２３および２
４・・・・・・抵抗、２５および２６・・・・・・可変
抵抗器。Figures 1a-'e are block diagrams of conventional separation adjustment circuits. Figure 2 is a block diagram of a separation adjustment circuit according to an embodiment of the present invention. 21 and 22... operational amplifiers; 23 and 2
4... Resistor, 25 and 26... Variable resistor.
Claims (1)
を有しかつステレオデコーダから出力される左側チャン
ネル信号電圧が非反転入力端子に印加される第１の演算
増幅器と、出力端子と反転入力端子との間に接続された
第２の抵抗を有しかつ前記ステレオデコーダから出力さ
れる右側チャンネル信号電圧が非反転入力端子に印加さ
れる第２の演算増幅器と、前記ステレオデコーダから出
力される右側チャンネル信号電圧を前記第１の淳算増幅
器の反転入力端子に印加する第１の可変抵抗器と、前記
ステレオデコーダから出力される左側チャンネル信号電
圧を前記第２の演算増幅器の反転入力端子に印加する第
２の可変抵抗器とを備えてなることを特徴とする分離度
調整回路。a first operational amplifier having a first resistor connected between the output terminal and the inverting input terminal and to which the left channel signal voltage output from the stereo decoder is applied to the non-inverting input terminal; a second operational amplifier having a second resistor connected between the inverting input terminal and the right channel signal voltage output from the stereo decoder is applied to the non-inverting input terminal; and an output from the stereo decoder. a first variable resistor that applies a right channel signal voltage to the inverting input terminal of the first Junsaku amplifier; and a first variable resistor that applies the left channel signal voltage output from the stereo decoder to the inverting input terminal of the second operational amplifier. and a second variable resistor that applies voltage to the terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14181681U JPS5848154U (en) | 1981-09-24 | 1981-09-24 | Separation degree adjustment circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14181681U JPS5848154U (en) | 1981-09-24 | 1981-09-24 | Separation degree adjustment circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5848154U true JPS5848154U (en) | 1983-03-31 |
Family
ID=29934882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14181681U Pending JPS5848154U (en) | 1981-09-24 | 1981-09-24 | Separation degree adjustment circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848154U (en) |
-
1981
- 1981-09-24 JP JP14181681U patent/JPS5848154U/en active Pending
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