JPS58147310U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS58147310U JPS58147310U JP4518982U JP4518982U JPS58147310U JP S58147310 U JPS58147310 U JP S58147310U JP 4518982 U JP4518982 U JP 4518982U JP 4518982 U JP4518982 U JP 4518982U JP S58147310 U JPS58147310 U JP S58147310U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- transistor
- input terminal
- control circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の一実施例を示す回路図である。
3・・・ミューティング用トランジスタ、4・・・制御
トランジスタ、5.6・・・時定数回路。The figure is a circuit diagram showing an embodiment of the present invention. 3... Muting transistor, 4... Control transistor, 5.6... Time constant circuit.
Claims (2)
用トランジスタと、複数のミューティング信号が夫々印
加されるミューティング信号入力端子と、該ミューティ
ング信号入力端子にミューティング信号が印加された際
前記ミューティング用トランジスタを導通させる制御回
路とを備え、該制御回路にて前記入力端子に印加される
ミューティング信号に応じて前記ミューティング用トラ
ンジスタの導通時間を可変するようにしたことを特徴と
するミューティング回路。(1) A muting transistor connected between a signal transmission path and ground, a muting signal input terminal to which a plurality of muting signals are respectively applied, and a muting signal applied to the muting signal input terminal. and a control circuit for making the muting transistor conductive, the control circuit varying the conduction time of the muting transistor according to a muting signal applied to the input terminal. muting circuit.
制御する1つの制御トランジスタと、異なる時定数を有
する2つの時定数回路より構成される実用新案登録請求
の範囲第(1)項記載のミューティング回路。(2) The muting circuit according to claim (1), wherein the control circuit comprises one control transistor that controls a muting transistor and two time constant circuits having different time constants.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4518982U JPS58147310U (en) | 1982-03-29 | 1982-03-29 | Muting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4518982U JPS58147310U (en) | 1982-03-29 | 1982-03-29 | Muting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58147310U true JPS58147310U (en) | 1983-10-04 |
Family
ID=30056222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4518982U Pending JPS58147310U (en) | 1982-03-29 | 1982-03-29 | Muting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58147310U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206740A (en) * | 1992-01-24 | 1993-08-13 | Matsushita Electric Ind Co Ltd | Muting device |
JP2007336310A (en) * | 2006-06-16 | 2007-12-27 | Onkyo Corp | Controller of sound mute circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5523587B2 (en) * | 1977-07-15 | 1980-06-24 |
-
1982
- 1982-03-29 JP JP4518982U patent/JPS58147310U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5523587B2 (en) * | 1977-07-15 | 1980-06-24 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206740A (en) * | 1992-01-24 | 1993-08-13 | Matsushita Electric Ind Co Ltd | Muting device |
JP2007336310A (en) * | 2006-06-16 | 2007-12-27 | Onkyo Corp | Controller of sound mute circuit |
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